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74FCT543ATQG8

P1-P3P4-P6P7-P7
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT543AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
1
OCTOBER 2009INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2009 Integrated Device Technology, Inc. DSC-5489/7
FEATURES:
• A, C, and D grades
• Low input and output leakage
≤≤
≤≤
≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility:
–VOH = 3.3V (typ.)
–VOL = 0.3V (typ.)
• High Drive outputs (-15mA IOH, 64mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Power off disable outputs permit "live insertion"
• Available in SOIC and QSOP packages
FUNCTIONAL BLOCK DIAGRAM
IDT74FCT543AT/CT/DT
FAST CMOS
OCTAL LATCHED
TRANSCEIVER
DESCRIPTION:
The FCT543T is a non-inverting octal transceiver built using an advanced
dual metal CMOS technology. This device contains two sets of eight D-type
latches with separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (CEAB) input must be low in order
to enter data from A0–A7 or to take data from B0–B7, as indicated in the
Function Table. With CEAB low, a low signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a subsequent low-to-
high transition of the LEAB signal puts the A latches in the storage mode and
their outputs no longer change with the A inputs. With CEAB and OEAB both
low, the 3-state B output buffers are active and reflect the data present at the
output of the A latches. Control of data from B to A is similar, but uses the
CEBA, LEBA and OEBA inputs.
A
1
Q
OEBA
A
2
A
3
A
4
A
5
A
6
A
7
B
1
B
2
B
3
B
4
B
5
B
6
B
7
CEBA
LEBA
OEAB
CEAB
LEAB
DETAIL A x 7
D
LE
Q
D
LE
DETAIL A
A
0
B
0
INDUSTRIAL TEMPERATURE RANGE
2
IDT74FCT543AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
PIN CONFIGURATION
Symbol Description Max Unit
VTERM
(2)
Terminal Voltage with Respect to GND –0.5 to +7 V
VTERM
(3)
Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature –65 to +150 ° C
I
OUT DC Output Current –60 to +120 mA
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
Symbol Parameter
(1)
Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 6 10 pF
C
OUT Output Capacitance VOUT = 0V 8 12 pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
SOIC/ QSOP
TOP VIEW
2
3
1
20
19
18
15
16
9
10
A6
A7
B6
B7
23
22
24
21
17
5
6
7
4
8
A1
OEBA
A
0
VCC
A2
A5
A3
A4
CEBA
B
2
B0
B1
B3
B4
B5
LEBA
13
14
11
12
CEAB
GND
LEAB
OEAB
PIN DESCRIPTION
Pin Names Description
OEAB A-to-B Output Enable Input (Active LOW)
OEBA B-to-A Output Enable Input (Active LOW)
CEAB A-to-B Enable Input (Active LOW)
CEBA B-to-A Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input (Active LOW)
LEBA B-to-A Latch Enable Input (Active LOW)
A0–A7 A-to-B Data Inputs or B-to-A 3-State Outputs
B0–B7 B-to-A Data Inputs or A-to-B 3-State Outputs
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT543AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
3
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
V
OH Output HIGH Voltage VCC = Min IOH = –8mA 2.4 3.3 — V
VIN = VIH or VIL IOH = –15mA 2 3 —
VOL Output LOW Voltage VCC = Min IOL = 64mA — 0.3 0.55 V
VIN = VIH or VIL
IOS Short Circuit Current VCC = Max., VO = GND
(3)
–60 –120 –225 mA
IOFF Input/Output Power Off Leakage
(5)
VCC = 0V, VIN or VO
≤≤
≤≤
≤
4.5V — — ±1µA
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
IIH Input HIGH Current
(4)
VCC = Max. VI = 2.7V — — ±1µA
IIL Input LOW Current
(4)
VCC = Max. VI = 0.5V — — ±1µA
IOZH High Impedance Output Current VCC = Max VO = 2.7V — — ±1µA
IOZL (3-State output pins)
(4)
VO = 0.5V — — ±1
II Input HIGH Current
(4)
VCC = Max., VI = VCC (Max.) — — ±1µA
VIK Clamp Diode Voltage VCC = Min, IIN = -18mA — –0.7 –1.2 V
VH Input Hysteresis — — 200 — mV
I
CC Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 0.01 1 mA
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%
FUNCTION TABLE
(1, 2)
For A-to-B (Symmetric with B-to-A)
Latch Output
Inputs Status Buffers
CEAB LEAB OEAB A-to-B B0–B7
H X X Storing High Z
X H X Storing X
X X H X High Z
L L L Transparent Current A Inputs
L H L Storing Previous* A Inputs
NOTES:
1. * Before LEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA
and OEBA.
P1-P3P4-P6P7-P7

74FCT543ATQG8

Mfr. #:
Buy 74FCT543ATQG8
Manufacturer:
IDT
Description:
Bus Transceivers Octal Latched Transeiver
Lifecycle:
New from this manufacturer.
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