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NB4L52MNG

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 3
1 Publication Order Number:
NB4L52/D
NB4L52
2.5 V/3.3 V/5.0 V Differential
Data/Clock D Flip-Flop
with Reset
Multi−Level Inputs to LVPECL Translator
w/ Internal Termination
The NB4L52 is a differential Data and Clock D flip−flop with a
differential asynchronous Reset. The differential inputs incorporate
internal 50 W termination resistors and will accept PECL, LVPECL,
LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock
transitions from Low to High, Data will be transferred to the
differential LVPECL outputs. The differential Clock inputs allow the
NB4L52 to also be used as a negative edge triggered device. The
device is housed in a small 3x3 mm 16 pin QFN package.
Features
• Maximum Input Clock Frequency > 4 GHz Typical
• 330 ps Typical Propagation Delay
• 145 ps Typical Rise and Fall Times
• Differential LVPECL Outputs, 750 mV Peak−to−Peak, Typical
• Operating Range: V
CC
= 2.375 V to 5.5 V with V
EE
= 0 V
• Internal Input Termination Resistors, 50 W
• Functionally Compatible with Existing 2.5 V/3.3 V/5.0 V LVEL,
LVEP, EP, and SG Devices
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
MARKING DIAGRAM*
http://onsemi.com
QFN−16
MN SUFFIX
CASE 485G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
16
NB4L
52
ALYWG
G
1
Data
Clock
Reset
VTD
VTCLK
D
CLK
VTR R
R D CLK Q
Hx x L
LL ZL
LH ZH
Z = LOW to HIGH Transition
x = Don’t Care
Table 1. TRUTH TABLE
Figure 1. Logic Diagram
D
VTD
CLK
VTCLK
VTRR
Q
Q
(Note: Microdot may be in either location)
1
NB4L52
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2
R
Figure 2. Pinout (Top View)
D
D
V
TD
V
TD
V
CC
Q
CLK
Q
V
TCLK
V
EE
1
2
3
4
5678
9
10
11
12
13141516
V
TR
R
CLK
NB4L52
V
TR
Exposed Pad (EP)
V
TCLK
Table 2. PIN DESCRIPTION
Pin Name I/O Description
1 V
TD
−
Internal 50 W Termination Pin. (See Table 4)
2 D ECL, CML, LVCMOS,
LVDS, LVTTL Input
Noninverted Differential Input. (Note 1)
3 D ECL, CML, LVCMOS,
LVDS, LVTTL Input
Inverted Differential Input. (Note 1)
4 V
TD
−
Internal 50 W Termination Pin. (See Table 4)
5 V
TCLK
−
Internal 50 W Termination Pin. (See Table 4)
6 CLK ECL, CML, LVCMOS,
LVDS, LVTTL Input
Noninverted Differential Input. (Note 1)
7 CLK ECL, CML, LVCMOS,
LVDS, LVTTL Input
Inverted Differential Input. (Note 1)
8 V
TCLK
−
Internal 50 W Termination Pin. (See Table 4)
9 V
EE
− Negative Supply Voltage
10 Q ECL Output
Inverted Differential Output. Typically terminated with 50 W resistor to V
CC
− 2.0 V.
11 Q ECL Output
Noninverted Differential Output. Typically terminated with 50 W resistor to V
CC
− 2.0 V.
12 V
CC
− Positive Supply Voltage
13 V
TR
−
Internal 50 W Termination Pin. (See Table 4)
14 R LVECL, LVCMOS,
LVTTL Input
Noninverted Differential Reset Input. (Note 1)
15 R LVECL, LVCMOS,
LVTTL Input
Inverted Differential Reset Input. (Note 1)
16 V
TR
−
Internal 50 W Termination Pin. (See Table 4)
− EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die
for improved heat transfer out of package. The pad is not electrically connected to the die,
but is recommended to be electrically and thermally connected to V
EE
on the PC board.
1. In the differential configuration when the input termination pin (VTD, VTD, VTR, VTR, VTCLK, VTCLK) are connected to a common
termination voltage or left open, and if no signal is applied on D/D
,CLK/CLK,R/R input then the device will be susceptible to self−oscillation.
NB4L52
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3
Table 3. ATTRIBUTES
Characteristic Value
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 1 kV
Moisture Sensitivity (Note 2) Pb Pkg Pb−Free Pkg
QFN−16 Level 1 Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 164
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Positive Power Supply V
EE
= 0 V 6.0 V
V
EE
Negative Power Supply V
CC
= 0 V −6.0 V
V
IO
Positive Input/Output
Negative Input/Output
V
EE
= 0 V
V
CC
= 0 V
V
I
v V
CC
V
I
w V
EE
6.0
−6.0
V
V
I
IN
Input Current Through R
T
(50 W Resistor)
Static
Surge
45
80
mA
mA
I
out
Output Current Continuous
Surge
25
50
mA
mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient) 0 LFPM
500 LFPM
16 QFN
16 QFN
42
35
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) 2S2P (Note 3) 16 QFN 4.0 °C/W
T
sol
Wave Solder Pb−Free 265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
P1-P3P4-P6P7-P8

NB4L52MNG

Mfr. #:
Buy NB4L52MNG
Manufacturer:
ON Semiconductor
Description:
Translation - Voltage Levels ANA ECL D FF W/DIFF RESET
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