MAX5934/MAX5934A
Positive High-Voltage, Hot-Swap Controllers with
Selectable Fault Management and Status Polarity
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In latch mode, the MAX5934/MAX5934A turn the
MOSFET off and keep it off after an overcurrent fault.
After the fault condition goes away and TIMER falls
below 0.5V, recycle the power supplies or toggle ON
low and high again to unlatch the device.
In autoretry mode, the MAX5934/MAX5934A turn the
MOSFET off after an overcurrent fault occurs. After the
fault condition is removed, the device waits for TIMER to
fall below 0.5V and then automatically restarts. If the fault
is due to an overtemperature condition, the MAX5934/
MAX5934A wait for the die temperature to cool down
below the +130°C threshold before restarting.
Power-Good (PWRGD_ ) Detection
The MAX5934/MAX5934A feature three power-good
outputs (PWRGD_) to indicate the status of three sepa-
rate voltages. PWRGD_ asserts if the device detects an
error condition.
PWRGD_ is true when FB_ voltages exceed the low-to-
high threshold voltage (V
FB_H
). PWRGD_ is false when
FB_ voltages go lower than the high-to-low threshold
voltage (V
FB_L
).
Connect external pullup resistors between PWRGD_
and OUT to pull up the PWRGD_ voltages to V
OUT
.
PWRGD2 can be used to indicate an overvoltage con-
dition on the main power-supply rail.
PWRGD3 asserts when GATE voltage has charged to
4.3V above the supply rail. PWRGD3 deasserts when
the TIMER voltage exceeds 1.233V threshold in response
to an extended fault condition.
The output polarity of PWRGD_ is determined by
POL_SEL. Drive POL_SEL high or leave it floating to
select PWRGD_ active high. Connect POL_SEL to GND
for PWRGD_ active low.
Undervoltage Lockout (UVLO)
The MAX5934A operates from a +9V to +80V supply
voltage range and has a default UVLO set at +8.3V.
The MAX5934 operates from a +33V to +80V supply
voltage range and has a default UVLO set at +31V. The
UVLO thresholds are adjustable using a resistive
divider connected to V
CC
(see R2 and R3 in Figure 5).
When the input voltage (or V
CC
) is below the UVLO
threshold, the MOSFET is held off. When the input volt-
age (or V
CC
) is above the UVLO threshold, the
MAX5934/MAX5934A go into normal operation (or
begin to turn on the external MOSFET).
To adjust the UVLO threshold, connect an external
resistive divider from V
IN
(or V
CC
) to ON and then from
ON to GND. The following equation is used to calculate
the new UVLO threshold:
V
UVLO_TH
= V
REF
(1 + (R2 / R3))
where V
REF
is typically 1.233V.
Applications Information
Hot-Circuit Insertion
The supply bypass capacitors on a circuit board can
draw high peak currents from the backplane power bus
as they charge when the circuit boards are inserted
into a live backplane. This can cause permanent dam-
age to the connector pins and glitch the system supply
causing other boards in the system to reset.
The MAX5934/MAX5934A are capable of controlling a
board’s power-supply voltage allowing for the safe
insertion or removal of a board from a live backplane.
These devices provide undervoltage and overcurrent
protection and power-good output signals (PWRGD_).
Overcurrent Protection
The MAX5934/MAX5934A provide sophisticated overcur-
rent protection to ensure robust operation under output-
current-transient and overcurrent fault conditions. The
current-protection circuit employs a foldback current limit
and a short-circuit or excessive output-current protection.
The MAX5934/MAX5934A offer a current foldback fea-
ture where the current folds back as a function of the
output voltage that is sensed at FB1. As Figure 6 illus-
trates, the voltage across R
SENSE
decreases linearly
when FB1 drops below 0.5V and stops at 12mV when
V
FB1
= 0V. The maximum current-limit equation is:
I
LIMIT
= 47mV / R
SENSE
For R
SENSE
= 0.025Ω, the current limit is set to 1.88A
and goes down to 480mA at short circuit (output short-
ed to GND).
In addition, the MAX5934/MAX5934A feature an
adjustable overcurrent response time. The required
time to regulate the MOSFET current depends on the
input capacitance of the MOSFET, GATE capacitor
(C1), compensation resistor (R1), and the internal delay
from SENSE to GATE. Figure 7 shows the propagation
delay from a voltage step at SENSE until GATE starts to
fall, as a function of overdrive.
