MAX2038CCQ+ Datasheet MAX2038CCQ+T, MAX2038CCQ+, MAX2038CCQ+D | P19-P21

MAX2038

Ultrasound VGA Integrated

with CW Octal Mixer

______________________________________________________________________________________ 19

Applications Information

Mode Select Response Time

The mode select response time is the time that the

device takes to switch between CW and VGA modes.

One possible approach to interfacing the CW outputs to

an instrumentation amplifier used to drive an ADC is

shown in Figure 2. In this implementation, there are four

large-value (in the range of 470nF to 1µF) capacitors

between each of the CW_IOUT+, CW_IOUT-,

CW_QOUT+, CW_QOUT- outputs and the circuitry they

are driving. The output of the CW mixer usually drives

the input of an instrumentation amplifier made up of op

amps whose input impedance is set by common-mode

setting resistors.

There are clearly both a highpass corner and a lowpass

corner present in this output network. The lowpass cor-

ner is set primarily by the 115Ω mixer pullup resistors,

the series 50Ω resistors, and the shunt 0.022µF capaci-

tor. This lowpass corner is used to filter a combination

of LO leakage and upper sideband. The highpass cor-

ner, however, is of a larger concern due to the fact that

it is dominated by the combination of a 1µF DC-block-

ing capacitor and the pair of shunt 31.6kΩ resistors.

If drawn, the simplified dominant highpass network

would look like Figure 3.

The highpass pole in this case is at f

= 1/(2 x pi x RC)

~ 5Hz. Note that this low highpass corner frequency is

required in order to filter the downconverted clutter tone,

which appears at DC, without interfering with CWD imag-

ing at frequencies as low as 400Hz. For example, if one

wanted to use CWD down to 400Hz, then a good choice

for the highpass pole would be at least a decade below

this (< 40Hz) as not to incur rolloff due to pole. Remember,

if the highpass pole is put at 400Hz, the response is 3dB

down at that corner frequency. The placement of the high-

pass pole at 5Hz in the above example is between the DC

and 40Hz limitations just discussed.

The bottom line is that any reasonably sized DC block

between the output of the mixer and the instrumentation

amplifier will pose a significant time constant that slows

the mode select switching speed.

An alternative solution to the approach in Figure 2,

which enables faster mode select response time, is

shown in Figure 4.

In Figure 4, the outputs of the CWD mixers are DC-

coupled into the inputs of the instrumentation ampli-

fiers. Therefore, the op amps must be able to accom-

modate the full compliance range of the mixer outputs,

which is a maximum of 11V when the mixers are dis-

abled, down to the 5V supply of the MAX2038 when the

mixers are enabled. The op amps can be powered from

11V for the high rail and 5V for the low rail, requiring a

6V op amp.

115Ω115Ω

1μF

0.022μF

31.6kΩ

50Ω

CW_IOUT+

CW_IOUT-

Figure 2. Typical Example of a CW Mixer’s Output Circuit

1μF

31.6kΩ

Figure 3. Simplified Circuit of Highpass Pole

+11V

+5V

Figure 4. Improved Mode Select Response Time Achieved with

DC-Coupled Input to Instrumentation Amplifier

MAX2038

Ultrasound VGA Integrated

with CW Octal Mixer

20 ______________________________________________________________________________________

Serial Interface

The serial interface of the MAX2038 programs the LO for

16, 8, or 4 quadrature phases using a serial shift register

implementation. Data is shifted into the device on DIN.

The serial shift register clock is applied to the CLK input.

The serial shift register has 5 bits per channel. The first 4

bits are for phase programming, and the fifth bit enables

or disables each channel of the mixer array.

Each mixer can be programmed to 1 of 16 phases;

therefore, 4 bits are required for each channel for pro-

gramming. The master high-frequency mixer clock is

applied to differential inputs LO_LVDS+ and LO_LVDS-

(for modes 1 and 2) and LO_ (for modes 3 and 4). The

LOAD input is provided to allow the user to load the

phase counters with the programming values to gener-

ate the correct LO phases. The input signals for mixing

are applied to the eight differential inputs, CWIN_+ and

CWIN_-. The summed I/Q baseband differential outputs

are provided on CW_IOUT+/- and CW_QOUT+/-.

CW_M1 and CW_M2 are used to select one of the four

possible modes of operation. See Table 1.

The serial interface is designed to allow multiple

devices to be easily daisy chained in order to minimize

program interface wiring. DOUT is available for this

daisy-chain function.

Programming the Beamformer

During normal CWD operation, the mixer clock at LO_ or

LO_LVDS+/- is on and the programming signals on DIN,

CLK, and LOAD are off. (LOAD = high, CLK = low, and

DIN = don’t care, but fixed to a high or low). To start the

programming sequence, turn off the mixer clock. Data is

shifted into the shift register at a recommended 10MHz

programming rate or 100ns minimum data clock

period/time. See Figure 5 for timing details.

After the shift registers are programmed, pull the LOAD

bus to logic-low and then back to logic-high to load the

internal counters into I/Q phase divider/selectors with

the proper values. LOAD must remain low for a mini-

mum time of t

CLH

. The user turns on the mixer clock to

start beamforming. The clock must turn on such that it

starts at the beginning of a mixer clock cycle.

DIN

CLK

LOAD

DCLKPWH

DCLKPWL

CLH

DCLK

DSU

HLD

LDMIXCLK

MIXER

CLOCK ON

MIXER

CLOCK ON

MIXER

CLOCK OFF

MIXER

CLOCK ON

MIXER

CLOCK OFF

MIXER

CLOCK OFF

MIXER

CLOCK ON

Figure 5. Shift Register Timing Diagram

MAX2038

Ultrasound VGA Integrated

with CW Octal Mixer

______________________________________________________________________________________ 21

CW Mixer Output Summation

The maximum differential current output is typically

3mA

P-P

and the mixer output compliance voltage

ranges from 4.75V to 12V per mixer channel. The mixer

common-mode current in each of the differential mixer

outputs is typically 3.25mA. The total summed current

would equal N x 3.25mA in each of the 115Ω load resis-

tors (where N = number of channels). In this case, the

quiescent output voltage at +V

SUM

and -V

SUM

outputs

would be 11V - (N x 3.25mA x 115) = 11V - (8 x 3.25mA

x 115) = 8.05V. The voltage swing at each output, with

one channel driven at max output current (differential

3mA

P-P

) while the other channels are not driven, would

be 1.5mA

P-P

x 115Ω or 174mV

P-P

and the differential

voltage would be 348mV

P-P

. The voltage compliance

range is defined as the valid range for +V

SUM

and -

SUM

in this example.

External Compensation

External compensation is required for bypassing inter-

nal biasing circuitry. Connect as close as possible a

4.7µF capacitor from EXT_C1, EXT_C2, and EXT_C3

(pins 13, 14, 15) to ground.

External Bias Resistor

An external resistor at EXT_RES is required to set the

bias for the internal biasing circuitry. Connect, as close

as possible, a 7.5kΩ (0.1%) resistor from EXT_RES (pin

38) to ground.

Analog Input and Output Coupling

In typical applications, the MAX2038 is being driven from

a low-noise amplifier (such as the MAX2034) and the

VGA is typically driving a discrete differential anti-alias fil-

ter into an ADC (such as the MAX1436 octal ADC). The

differential input impedance of the MAX2038 is typically

240Ω. The differential outputs of the VGA are capable of

driving a differential load capacitance to GND at each of

the VGA differential outputs of 60pF, and differential

capacitance across the VGA outputs is 10pF, R

1kΩ. The differential outputs have a common-mode

bias of approximately 3.75V. AC-couple these differen-

tial outputs if the next stage has a different common-

mode input range.

Ultrasound-Specific IMD3 Specification

Unlike typical communications specifications, the two

input tones are not equal in magnitude for the ultra-

sound-specific IMD3 two-tone specification. In this

measurement, f

represents reflections from tissue and

represents reflections from blood. The latter reflec-

tions are typically 25dB lower in magnitude, and hence

the measurement is defined with one input tone 25dB

lower than the other. The IMD3 product of interest (f

- f

)) presents itself as an undesired Doppler error

signal in ultrasound applications. See Figure 6.

Board Layout

The pin configuration of the MAX2038 is optimized to

facilitate a very compact physical layout of the device

and its associated discrete components. A typical

application for this device might incorporate several

devices in close proximity to handle multiple channels

of signal processing.

The exposed pad (EP) of the MAX2038’s TQFP-EP

package provides a low thermal-resistance path to the

die. It is important that the PCB on which the MAX2038

is mounted be designed to conduct heat from the EP.

In addition, provide the EP with a low-inductance path

to electrical ground. The EP MUST be soldered to a

ground plane on the PCB, either directly or through an

array of plated via holes.

-25dB

ULTRASOUND

IMD3

- (f

- f

+ (f

- f

Figure 6. Ultrasound IMD3 Measurement Technique

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

MAX2038CCQ+

Mfr. #:

Buy MAX2038CCQ+

Manufacturer:

Maxim Integrated

Description:

Instrumentation Amplifiers Ultrasound Variable Gain Amplifie

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MAX2038CCQ+

MAX2038CCQ+

Products related to this Datasheet