Document #: 001-06458 Rev. *B Page 2 of 9
Pinouts
Figure 1. 6-Pin Ceramic LCC
Functional Description
The CY2V014 is a high-performance high-frequency
voltage-controlled crystal oscillator (VCXO).
The device uses a Cypress proprietary low-noise PLL to
synthesize the frequency from an embedded crystal.
The output frequency is user adjustable by means of an analog
control voltage applied to the V
IN
pin.
VCXO Control Voltage (V
IN
, pin 1)
V
IN
is an analog input that is used to adjust the output frequency.
The nominal output frequency is defined when V
IN
= V
DD
/2.
Increasing the voltage on V
IN
increases the output frequency,
while decreasing the voltage on V
IN
decreases the output
frequency. Any voltage between V
SS
and V
DD
is allowed on V
IN
.
The voltage/frequency slope is very linear over most of the
control voltage range.
Programming Description
Field-Programmable CY2V014
Field-programmable devices are shipped unprogrammed, and
must be programmed before use. Customers can use Cyber-
Clocks™ Online Software to specify the device configuration and
generate a .JED programming file. Programming of samples and
prototype quantities is available using the CY3672 programmer.
Third-party vendors manufacture programmers for small to large
volume applications. Cypress’s value-added distribution
partners also provide programming services. Field-program-
mable devices are designated with an “F” in the part number, and
are intended for quick prototyping and inventory reduction.
Factory-Configured CY2V014
For customers wanting ready-to-use devices, the CY2V014 is
available factory-configured, with no programming required. All
requests must be submitted to the local Cypress Field Appli-
cation Engineer (FAE) or sales representative. Once the request
has been processed, you will receive a new part number,
samples, and data sheet with the programmed values. This part
number will be used for additional sample requests and
production orders.
Programming Variables
Output Frequency
Any frequency between 50 MHz and 690 MHz may be specified.
Absolute Pull Range
The absolute pull range (APR) may be specified.
Pin 2: Output Enable or Power-Down (OE/PD#)
Pin 2 can be programmed as either output enable (OE) or
Power-down (PD#). The OE function is used to enable or disable
the CLK output very quickly, but it does not reduce core power
consumption. The PD# function puts the device into a low-power
state, but wake-up takes longer because the PLL must reacquire
lock.
1
3
VIN
VSS
VDD
CLK
6
4
2 5CLK#OE/PD#
Pin Definitions
Pin Name I/O Type Description
1V
IN
Analog Input VCXO control voltage. Positive slope.
2 OE/PD# CMOS Input, internal
pull-up
Output Enable pin: Active HIGH. If OE = 1, CLK is enabled.
Power-down pin: Active LOW. If PD# = 0, Power-down is enabled.
The functionality of this pin is programmable.
3V
SS
Power Power supply ground
4, 5 CLK, CLK# Output Clock output. LVPECL outputs. CLK# is the complement of CLK.
6V
DD
Power Positive power supply: 2.5 V or 3.3 V
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