UJA1079_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 25 of 45
NXP Semiconductors
UJA1079
LIN core system basis chip
7. Limiting values
Table 8. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
x
voltage on pin x DC value
pins V1 and INTN −0.3 7 V
pins EN, SDI, SDO, SCK, SCSN, TXDL, RXDL,
RSTN and WDOFF
−0.3 V
V1
+ 0.3 V
pin VEXCC V
V1
− 0.3 V
V1
+ 0.35 V
pins WAKE1, WAKE2, WBIAS and LIN;
with respect to any other pin
−58 +58 V
pin LIMP and BAT −0.3 +40 V
pin VEXCTRL −0.3 V
BAT
+ 0.3 V
pin DLIN; with respect to any other pin V
BAT
− 0.3 +58 V
I
R(V1-BAT)
reverse current from
pin V1 to pin BAT
V
V1
≤ 5V
[1]
- 250 mA
I
DLIN
current on pin DLIN −65 0 mA
V
trt
transient voltage on pins
BAT: via reverse polarity diode/capacitor
LIN: coupling via 1 nF capacitor
DLIN: via 1 kW resistor
[2]
−150 +100 V
V
ESD
electrostatic
discharge voltage
IEC 61000-4-2
[3]
pins BAT with capacitor and LIN; via a series
resistor on pins DLIN, WAKE1, WAKE2, LIMP and
WBIAS; via transistor on pin VEXCTRL
[4]
−6+6kV
HBM
[5]
pins LIN, DLIN, WAKE1 and WAKE2
[6]
−8+8kV
pin BAT; referenced to ground −4+4kV
pin TEST2; referenced to pin BAT −1.25 +2 kV
pin TEST2; referenced to other reference pins −2+2kV
any other pin −2+2kV
MM
[7]
any pin −300 +300 V
CDM
[8]
corner pins −750 +750 V
any other pin −500 +500 V
T
vj
virtual junction
temperature
[9]
−40 +150 °C
T
stg
storage temperature −55 +150 °C
