REVISION D 04/28/16 9 6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
9DBV0641 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
Electrical Characteristics–Phase Jitter Parameters
TA = T
AMB
; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
-3dB point in High BW Mode
1.8 2.7 3.8
MHz 1,5
-3dB point in Low BW Mode
0.8 1.4 2
MHz 1,5
PLL Jitter Peaking t
JPEAK
Peak Pass band Gain
1.3 2
dB 1
Duty Cycle t
D
Measured differentially, PLL Mode 45 50.1 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, Bypass Mode @100MHz -1 0 1 % 1,3
t
dBYP
= 50% 3000 3600 4500 ps 1
t
dPLL
= 50% 0 -4 200 ps 1,4
Skew, Output to Output t
sk3
= 50% 39 50 ps 1,4
PLL mode 14 50 ps 1,2
Additive Jitter in Bypass Mode 0.1 5 ps 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform
3
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4
All outputs at default slew rate
5
The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
Skew, Input to Output
Jitter, Cycle to cycle t
jcyc-cyc
PLL Bandwidth BW
TA = T
AMB
; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
INDUSTRY
hPCIeG1
PCIe Gen 1 31 52 86 ps (p-p) 1,2,3,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.8 1.4 3
ps
(rms)
1,2,3,5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
2.3 2.5
3.1
ps
(rms)
1,2,3,5
t
jphPCIeG3
PCIe Gen 3 Common Clock Architecture
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
0.5 0.6
1
ps
(rms)
1,2,3,5
t
jphPCIeG3SRn
S
PCIe Gen 3 Separate Reference No Spread (SRnS)
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
0.5 0.6
0.7
ps
(rms)
1,2,3,5
t
jphSGMII
125MHz, 1.5MHz to 20MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
1.9
2N/A
ps
(rms)
1,2,3,5
t
jphPCIeG1
PCIe Gen 1 0.1 5 N/A
ps
(p-p)
1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.1 0.4 N/A
ps
(rms)
1,2,5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.01 0.4 N/A
ps
(rms)
1,2,5
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.00 0.1 N/A
ps
(rms)
1,2,4,5
t
jphSGMIIM0
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
165 200 N/A
fs
(rms)
1,6
t
jphSGMIIM1
125MHz, 12kHz to 20MHz, -20dB/decade rollover
< 1.5MHz, -40db/decade rolloff > 10MHz
251 300 N/A
fs
(rms)
1,6
1
Guaranteed by design and characterization, not 100% tested in production.
4
For RMS fi
ures, additive jitter is calculated by solvin
the followin
equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
5
Driven by 9FGV0831 or equivalent
6
Rohde&Schartz SMA100
2
See htt
://www.
cisi
.com for com
lete s
ecs
Sam
le size of at least 100K c
cles. This fi
ures extra
olates to 108
s
k-
k @ 1M c
cles for a BER of 1-12.
Additive Phase Jitter
t
jphPCIeG2
Phase Jitter, PLL Mode
t
jphPCIeG2