DATASHEET
LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ICS670-02
IDT™ / ICS™
LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 1
ICS670-02 REV J 051310
Description
The ICS670-02 is a high speed, low phase noise, Zero
Delay Buffer (ZDB) which integrates IDT’s proprietary
analog/digital Phase Locked Loop (PLL) techniques. Part of
IDT’s ClockBlocks
TM
family, the part’s zero delay feature
means that the rising edge of the input clock aligns with the
rising edges of the outputs giving the appearance of no
delay through the device. There are two identical outputs on
the chip. The FBCLK should be used to connect to the
FBIN. Each output has its own output enable pin.
The ICS670-02 is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to video. By allowing off-chip feedback
paths, the chip can eliminate the delay through other
devices. The 15 different on-chip multipliers work in a
variety of applications. For other multipliers, including
functional multipliers, see the ICS527.
Features
• Packaged in 16-pin SOIC
• Pb (lead) free package, RoHS compliant
• Clock inputs from 5 to 160 MHz (see page 2)
• Patented PLL with low phase noise
• Output clocks up to 160 MHz at 3.3 V
• 15 selectable on-chip multipliers
• Power down mode available
• Low phase noise: -111 dBc/Hz at 10 kHz
• Output enable function tri-states outputs
• Low jitter 15 ps one sigma
• Advanced, low power, sub-micron CMOS process
• Operating voltage of 3.3 V or 5 V
• Industrial temperature range available (-40 to +85°C)
Block Diagram
Divide by
N
Voltage
Controlled
Oscillator
FBCLK
OE1
Phase
Detector,
Charge
Pump, and
Loop Filter
FBIN
S3:S0
ICLK
CLK2
4
OE2
VDD
3
GND
3
External Feedback from FBCLK is recommended.