Z86C61/62/96
CMOS Z8 Microcontroller Zilog
34 P R E L I M I N A R Y DS97Z8X1600
FUNCTIONAL DESCRIPTION (Continued)
Clock. The Z86C61/62/96 on-chip oscillator has a high-
gain, parallel-resonant amplifier for connection to a crystal,
LC, ceramic resonator, or any suitable external clock
source (XTAL1 = Input, XTAL2 = Output). The crystal
should be AT cut, 1 MHz to 20 MHz max, and series resis-
tance (RS) is less than or equal to 100 Ohms. The crystal
should be connected across XTAL1 and XTAL2 using the
recommended capacitors (10 pF < CL < 100 pF) from each
pin to device ground (Figure 27).
Note: Actual capacitor values specified by the crystal
manufacturer.
HALT. Turns off the internal CPU clock but not the XTAL
oscillation. The counter/timers and the external interrupts
IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The devices
are recovered by interrupts, either externally or internally
generated. An interrupt request must be executed (en-
abled) to exit HALT mode. After the interrupt service rou-
tine, the program continues from the instruction after the
HALT.
STOP. This instruction turns off the internal clock and ex-
ternal crystal oscillation and reduces the standby current
to 5 µA (typical) or less. The STOP mode is terminated by
a reset, which causes the processor to restart the applica-
tion program at address 000CH.
In order to enter STOP (or HALT) mode, it is necessary to
first flush the instruction pipeline to avoid suspending exe-
cution in mid-instruction. To do this, the user must execute
a NOP (opcode=0FFH) immediately before the appropri-
ate sleep instruction, i.e.,
Figure 27. Oscillator Configuration
XTAL1
XTAL2
C1
C2
C1
C2
XTAL1
XTAL2
XTAL1
XTAL2
Ceramic Resonator
or Crystal
LC Clock
External Clock
L
FF NOP ; clear the pipeline
6F STOP ; enter STOP mode
or
FF NOP ; clear the pipeline
7F HALT ; enter HALT mode
PS003501-0301
Z86C61/62/96
Zilog CMOS Z8 Microcontroller
DS97Z8X1600 P R E L I M I N A R Y 35
1
Z8 CONTROL REGISTER DIAGRAMS
Figure 28. Serial I/O Register
(F0H: Read/Write)
Figure 29. Timer Mode Register
(F1H: Read/Write)
Figure 30. Counter/Timer1 Register
(F2H: Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Serial Data (D0 = LSB)
R240 SIO
D7 D6
D5
D4 D3 D2 D1 D0
0 Disable T0 Count
1 Enable T0 Count
0 No Function
1 Load T0
0 No Function
1 Load T1
0 Disable T1 Count
1 Enable T1 Count
TIN Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
TOUT Modes
00 Not Used
01 T0 Out
10 T1 Out
11 Internal Clock Out
R241 TMR
D7
D6
D5 D4 D3
D2
D1 D0
T1 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T1 Current Value
(When Read)
R242 T1
Figure 31. Prescaler 1 Register
(F3H: Write Only)
Figure 32. Counter/Timer 0 Register
(F4H: Read/Write)
Figure 33. Prescaler 0 Register
(F5H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Count Mode
0 T1 Single Pass
1 T1 Modulo N
Clock Source
1 T1 Internal
0 T1 External Timing Input
(TIN) Mode
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R243 PRE1
D7 D6
D5
D4 D3 D2 D1 D0
T0 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T0 Current Value
(When Read)
R244 T0
0 T0 Single Pass
1 T0 Modulo N
D7 D6 D5 D4 D3 D2 D1 D0
Count Mode
Reserved (Must be 0)
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R245 PRE0
PS003501-0301
Z86C61/62/96
CMOS Z8 Microcontroller Zilog
36 P R E L I M I N A R Y DS97Z8X1600
Z8 CONTROL REGISTER DIAGRAMS (Continued)
Figure 34. Port 2 Mode Register
(F6H: Write Only)
Figure 35. Port 3 Mode Register
(F7H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
P20 - P27 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input
R246 P2M
D7 D6 D5 D4 D3 D2 D1 D0
R247 P3M
0 Port 2 Open Drain
1 Port 2 Push-pull
0 Parity Off
1 Parity On
0 P32 = Input
P35 = Output
1 P32 = /DAV0/RDY0
P35 = RDY0//DAV0
0 P31 = Input (TIN)
P36 = Output (TOUT)
1 P31 = /DAV2/RDY2
P36 = RDY2//DAV2
0 P30 = Input
P37 = Output
1 P30 = Serial In
P37 = Serial Out
Reserved (Must be 0)
00 P33 = Input
P34 = Output
01 P33 = Input
10 P34 = /DM
P33 = /DAV1/RDY1
P34 = RDY1//DAV1
11
Figure 36. Port 0 and 1 Mode Register
(F8H: Write Only)
Figure 37. Interrupt Priority Register
(F9H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
R248 P01M
P0
0
- P0
0
Mode
00 Output
01 Input
1X A
11
- A
8
Stack Selection
0 External
1 Internal
P1
7
- P1
0
Mode
00 Byte Output
01 Byte Input
10 AD
7
- AD
0
11 High-Impedance AD
7
- DA
0
,
/AS, /DS, /R//W, A
11
- A
8
,
A
15
- A
12
, If Selected
P0
7
- P0
4
Mode
00 Output
01 Input
1X A
15
- A
12
Reserved (Must be 0)
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
Reserved = 000
C > A > B = 001
A > B > C = 010
A > C > B = 011
B > C > A = 100
C > B > A = 101
B > A > C = 110
Reserved = 111
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
Reserved (Must be 0)
R249 IPR
PS003501-0301

Z86C9620VSG

Mfr. #:
Manufacturer:
ZiLOG
Description:
8-bit Microcontrollers - MCU 20MHz ROMLESS
Lifecycle:
New from this manufacturer.
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