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2.3. Do I really need an RC lter on the input? What is it for? Are other
values of R and C okay?
The input anti-aliasing lter (R=39 Ω, C=0.01 μF)
shown in the typical application circuit is recom-
mended for ltering fast switching voltage transients
from the input signal. (This helps to attenuate higher
signal frequencies which could otherwise alias with
the input sampling rate and cause higher input oset
voltage.)
Some issues to keep in mind using dierent lter
resistors or capacitors are:
1. Filter resistor: Input bias current for pins 2 and 3:
This is on the order of 500 nA. If you are using a
single lter resistor in series with pin 2 but not pin
3 the IxR drop across this resistor will add to the
oset error of the device. As long as this IR drop
is small compared to the input oset voltage
there should not be a problem. If larger-valued
resistors are used in series, it is better to put half
of the resistance in series with pin 2 and half the
resistance in series with pin 3. In this case, the
oset voltage is due mainly to resistor mismatch
(typically less than 1% of the resistance design
value) multiplied by the input bias.
2. Filter resistor: The equivalent input resistance
for ACPL-C78A/C780/C784 is around 500 kΩ.
It is therefore best to ensure that the lter
resistance is not a signicant percentage of
this value; otherwise the oset voltage will be
increased through the resistor divider eect.
[As an example, if R
lt
= 5.5 kΩ, then V
OS
= (Vin *
1%) = 2 mV for a maximum 200 mV input and V
OS
will vary with respect to Vin.]
3. The input bandwidth is changed as a result of this
dierent R-C lter conguration. In fact this is one
of the main reasons for changing the input-lter
R-C time constant.
4. Filter capacitance: The input capacitance of the
ACPL-C78A/C780/C784 is approximately 1.5 pF.
For proper operation the switching input-side
sampling capacitors must be charged from a
relatively xed (low impedance) voltage source.
Therefore, if a lter capacitor is used it is best for
this capacitor to be a few orders of magnitude
greater than the C
INPUT
(A value of at least 100 pF
works well.)
2.4. How do I ensure that the ACPL-C78A/C780/C784 is not destroyed
as a result of short circuit conditions which cause voltage drops
across the sense resistor that exceed the ratings of the ACPL-
C78A/C780/C784’s inputs?
Select the sense resistor so that it will have less than 5 V
drop when short circuits occur. The only other require-
ment is to shut down the drive before the sense resistor
is damaged or its solder joints melt. This ensures that
the input of the ACPL-C78A/C780/C784 can not be
damaged by sense resistors going open-circuit.
3. Isolation and insulation
3.1. How many volts will the ACPL-C78A/C780/C784 withstand?
The momentary (1 minute) withstand voltage is 5000
V rms per UL 1577 and CSA Component Acceptance
Notice #5.
4. Accuracy
4.1. Can the signal to noise ratio be improved?
Yes. Some noise energy exists beyond the 100 kHz
bandwidth of the ACPL-C78A/C780/C784. Additional
ltering using dierent lter R,C values in the post-am-
plier application circuit can be used to improve the
signal to noise ratio. For example, by using values of R3
= R4 = 10 kΩ, C5 = C6 = 470 pF in the application circuit
the rms output noise will be cut roughly by a factor of
2. In applications needing only a few kHz bandwidth
even better noise performance can be obtained. The
noise spectral density is roughly 500 nV/sqrt(Hz) below
20 kHz (input referred).
4.2. Does the gain change if the internal LED light output degrades
with time?
No. The LED is used only to transmit a digital pattern.
Avago Technologies has accounted for LED degrada-
tion in the design of the product to ensure long life.
5. Power supplies and start-up
5.1. What are the output voltages before the input side power supply
is turned on?
V
OUT+
is close to 1.29 V and V
OUT–
is close to 3.80 V. This
is equivalent to the output response at the condition
that LED is completely o.
5.2. How long does the ACPL-C78A/C780/C784 take to begin working
properly after power-up?
Within 1 ms after V
DD1
and V
DD2
powered the device
starts to work. But it takes longer time for output to
settle down completely. In case of the oset mea-
surement while both inputs are tied to ground there
is initially V
OS
adjustment (about 60 ms). The output
completely settles down in 100 ms after device
powering up.
6. Miscellaneous
6.1. How does the ACPL-C78A/C780/C784 measure negative signals
with only a +5 V supply?
The inputs have a series resistor for protection
against large negative inputs. Normal signals are no
more than 200 mV in amplitude. Such signals do not
forward bias any junctions suciently to interfere
with accurate operation of the switched capacitor
input circuit.
