UBA2035_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 31 October 2008 5 of 13
NXP Semiconductors
UBA2035
HF Full bridge control IC for HID lighting
[1] If pin DD = 0 the bridge enters the state (oscillation state and pin BD = 0 and pin SU = 1) in the predefined
position: V
GHL
=V
FSL
, V
GLR
=V
VDD
, V
GLL
=V
PGND
and V
GHR
=V
SHR
.
[2] Only if the level of pin CLK changes from logical 1 to 0, the level of outputs GHL, GHR, GLL and GLR
changes.
If there is no external clock available, the internal oscillator can be used. The design
equation for the bridge oscillator frequency is shown in Equation 1.
(1)
R
osc
and C
osc
are external components connected to the RC pin (R
osc
connected to pin
VDD and C
osc
connected to pin SGND). In this situation the pins V
DD(CLK)
, CLK, and
V
SS(CLK)
can be connected to SGND.
The clock signal, either coming from pin RC or pin CLK, can be divided by two in order to
obtain a 50 % duty cycle gate drive signal. This can be achieved by applying a voltage to
the DD input lower than V
IL(DD)
(e.g. connect pin DD to pin SGND).
7.4 Non-overlap time
In the full bridge configuration the non-overlap time is defined as the time between turning
off the two conducting MOSFETs and turning on the two other MOSFETs. The (very
small) non-overlap time is internally fixed to t
no
, which allows a HID system to operate with
a very small phase angle between the load current and the full bridge voltage (pins SHL
and SHR). This can be beneficial for HID systems in which the lamp is ignited via a
resonance network.
7.5 Start-up delay
A simple resistor-capacitor (RC) filter (R between pin VDD and pin SU; C between pin SU
and pin SGND) or a control signal from a processor can be used to create a start-up
delay. This can be beneficial for those applications in which building up the high voltage
takes more time. A start-up delay will ensure that the HID system will not start up before
this high voltage has been reached.
Table 3. Driver
Gate driver output voltages as function of the logical levels at the pins BD, SU, DD and CLK.
Device
state
BD SU DD CLK GHL GHR GLL GLR
Start-up
state
1 - - - 0 (= V
SHL
) 0 (= V
SHR
) 0 (= V
PGND)
0 (= V
PGND
)
0 - - - 0 (= V
SHL
) 0 (= V
SHR
) 1 (= V
VDD
) 1 (= V
VDD
)
Oscillation
state
1 - - - 0 (= V
SHL
) 0 (= V
SHR
) 0 (= V
PGND
) 0 (= V
PGND
)
0 0 - - 0 (= V
SHL
) 0 (= V
SHR
) 1 (= V
VDD
) 1 (= V
VDD
)
0 1 1 1 0 (= V
SHL
) 1 (= V
FSR
) 1 (= V
VDD
) 0 (= V
PGND
)
0 1 1 0 1 (= V
FSL
) 0 (= V
SHR
) 0 (= V
PGND
) 1 (= V
VDD
)
01 0
[1]
1 → 0
[2]
GHL GHR GLL GLR
f
bridge
1
K
osc
R
osc
× C
osc
×
---------------------------------------------
=
