IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
8
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(4)
AC Test Conditions
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns Max.
1.5V
1.5V
Figures 1 and 2
2940 tbl 11
Figure 1. AC Output Test Load
2940 drw 06
893Ω
30pF
347Ω
5V
DATA
OUT
BUSY
INT
893Ω
5pF*
347Ω
5V
DATA
OUT
2940 drw 05
7007X15
Com'l Only
7007X20
Com'l & Ind
7007X25
Com'l, Ind
& Military
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 15
____
20
____
25
____
ns
t
AA
Address Access Time
____
15
____
20
____
25 ns
t
ACE
Chip Enable Access Time
(3)
____
15
____
20
____
25 ns
t
AOE
Output Enable Access Time
____
10
____
12
____
13 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
12
____
15 ns
t
PU
Chip Enable to Power Up Time
(2 )
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2 )
____
15
____
20
____
25 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
12
____
ns
t
SAA
Semaphore Address Access Time
____
15
____
20
____
25 ns
2940 tbl 12a
7007X35
Com'l, Ind
& Military
7007X55
Com'l, Ind
& Military
UnitSymbol Parameter Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 35
____
55
____
ns
t
AA
Address Access Time
____
35
____
55 ns
t
ACE
Chip Enable Access Time
(3 )
____
35
____
55 ns
t
AOE
Output Enable Access Time
____
20
____
30 ns
t
OH
Output Hold from Address Change 3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
25 ns
t
PU
Chip Enable to Power Up Time
(2 )
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2 )
____
35
____
50 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)15
____
15
____
ns
t
SAA
Semaphore Address Access Time
____
35
____
55 ns
2940 tbl 12b