83904-02 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 17, 201610
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT SKEW
20%
80%
80%
20%
t
R
t
F
Q0:Q3
PARAMETER MEASUREMENT INFORMATION, CONTINUED
83904-02 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 17, 201611
APPLICATION INFORMATION
INPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left fl oating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
CLK I
NPUT
For applications not requiring the use of the clock input, it can be
left fl oating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK input to ground.
S
ELECT PINS
All select pins have internal pull-ups and pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUTS
All unused LVCMOS output can be left fl oating. There should be
no trace attached.
83904-02 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 17, 201612
FIGURE 1. CRYSTAL INPUT INTERFACE
CRYSTAL INPUT INTERFACE
Figure 1 shows an example of 83904-02 crystal interface with
a parallel resonant crystal. The frequency accuracy can be fi ne
tuned by adjusting the C1 and C2 values. For a parallel crystal with
loading capacitance CL = 18pF, we suggest C1 = 15pF and C2 =
15pF to start with. These values may be slightly fi ne tuned further to
optimize the frequency accuracy for different board layouts. Slightly
increasing the C1 and C2 values will slightly reduce the frequency.
Slightly decreasing the C1 and C2 values will slightly increase the
frequency. For the oscillator circuit below, R1 can be used, but is not
required. For new designs, it is recommended that R1 not be used.
OVERDRIVING THE CRYSTAL INTERFACE
The XTAL_IN input can a single-ended LVCMOS signal through
an AC coupling capacitor. A general interface diagram is shown in
Figure 2A. The XTAL_OUT pin can be left fl oating. The maximum
amplitude of the input signal should not exceed 2V and the input
edge rate can be as slow as 10ns. This confi guration requires that
the output impedance of the driver (Ro) plus the series resistance
(Rs) equals the transmission line impedance. In addition, matched
FIGURE 2A. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
C1
15p
R1 (optional)
0
X1
18pF Parallel Cry stal
C2
15p
XTAL _I N
XTAL _O U T
FIGURE 2A. GENERAL DIAGRAM FOR LVPECL DRIVER TO XTAL INPUT INTERFACE
R2
100
R1
100
RS 43
Ro ~ 7 Ohm
Driv er_LVCMOS
Zo = 50 Ohm
C1
0.1uF
3.3V
3.3V
Cry stal Input Interf ace
XTAL_IN
XTAL_OUT
Cry stal Input Interf ace
XTAL_IN
XTAL_OUT
R3
50
C1
0.1uF
R2
50
R1
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
VCC=3.3V
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50Ω applications,
R1 and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω. By overdring the crystal oscillator, the device
will be functional, but note, the device performance is guaranteed
by using a quartz crystal.

83904AG-02LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer Fanout Buffer,2-XTAL /LVCMOS Input
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet