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1732FS–ATARM–12-Apr-06
AT91R40008
5. Architectural Overview
The AT91R40008 microcontroller integrates an ARM7TDMI with EmbeddedICE interface,
memories and peripherals. The architecture consists of two main buses: the Advanced Sys-
tem Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for maximum performance
and controlled by the memory controller, the ASB interfaces the ARM7TDMI processor with
the on-chip 32-bit memories, the External Bus Interface (EBI) and the AMBA
™
Bridge. The
AMBA Bridge drives the APB, which is designed for accesses to on-chip peripherals and opti-
mized for low power consumption.
The AT91R40008 microcontroller implements the ICE port of the ARM7TDMI processor on
dedicated pins, offering a complete, low-cost and easy-to-use debug solution for target
debugging.
5.1 Memories
The AT91R40008 microcontroller embeds 256K bytes of internal SRAM. The internal memory
is directly connected to the 32-bit data bus and is single-cycle accessible.
The AT91R40008 microcontroller features an External Bus Interface (EBI), which enables
connection of external memories and application-specific peripherals. The EBI supports 8- or
16-bit devices and can use two 8-bit devices to emulate a single 16-bit device. The EBI imple-
ments the early read protocol, enabling faster memory accesses than standard memory
interfaces.
5.2 Peripherals
The AT91R40008 microcontrollers integrate several peripherals, that are classified as system
or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and can
be programmed with a minimum number of instructions. The peripheral register set consists of
control, mode, data, status and enable/disable/status registers.
An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs and
on- and off-chip memories address space without processor intervention. Most importantly,
the PDC removes the processor interrupt handling overhead, making it possible to transfer up
to 64K contiguous bytes without reprogramming the start address, thus increasing the perfor-
mance of the microcontroller and reducing the power consumption.
5.2.1 System Peripherals
The External Bus Interface (EBI) controls the external memory or peripheral devices via an 8-
or 16-bit data bus and is programmed through the Advanced Peripheral Bus (APB). Each chip
select line has its own programming register.
The Power-saving (PS) module implements the Idle mode (ARM7TDMI core clock stopped
until the next interrupt) and enables the user to adapt the power consumption of the microcon-
troller to application requirements (independent peripheral clock control).
The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the inter-
nal peripherals and the four external interrupt lines (including the FIQ) to provide an interrupt
and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller and,
using the Auto-vectoring feature, reduces the interrupt latency time.
The Parallel Input/Output Controller (PIO) controls up to 32 I/O lines. It enables the user to
select specific pins for on-chip peripheral input/output functions and general-purpose
