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74VHC74FT

P1-P3P4-P6P7-P9
74VHC74FT
1
CMOS Digital Integrated Circuits Silicon Monolithic
74VHC74FT
74VHC74FT
74VHC74FT
74VHC74FT
Start of commercial production
2013-05
1.
1.
1.
1. Functional Description
Functional Description
Functional Description
Functional Description
• Dual D-Type Flip-Flop with Preset and Clear
2.
2.
2.
2. General
General
General
General
The 74VHC74FT is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate C
2
MOS technology.
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS
low power dissipation.
The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of
the CK pulse.
CLR and PR are independent of the CK and are accomplished by setting the appropriate input low.
An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply
voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up.
This circuit prevents device destruction due to mismatched supply and input voltages.
3.
3.
3.
3. Features
Features
Features
Features
(1) AEC-Q100 (Rev. H) (Note 1)
(2) Wide operating temperature range: T
opr
= -40 to 125
(3) High speed: f
MAX
= 170 MHz (typ.) at V
CC
= 5.0 V
(4) Low power dissipation: I
CC
= 2.0 µA (max) at T
a
= 25
(5) High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min)
(6) Power-down protection is provided on all inputs.
(7) Balanced propagation delays: t
PLH
≈ t
PHL
(8) Wide operating voltage range: V
CC(opr)
= 2.0 V to 5.5 V
(9) Pin and function compatible with the 74 series (74AC/HC/AHC etc.) 74 type.
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales
representative.
4.
4.
4.
4. Packaging
Packaging
Packaging
Packaging
TSSOP14B
2017-02-22
Rev.5.0
©2016 Toshiba Corporation
74VHC74FT
2
5.
5.
5.
5. Pin Assignment
Pin Assignment
Pin Assignment
Pin Assignment
6.
6.
6.
6. Marking
Marking
Marking
Marking
7.
7.
7.
7. IEC Logic Symbol
IEC Logic Symbol
IEC Logic Symbol
IEC Logic Symbol
8.
8.
8.
8. Truth Table
Truth Table
Truth Table
Truth Table
X: Don't care
2017-02-22
Rev.5.0
©2016 Toshiba Corporation
74VHC74FT
3
9.
9.
9.
9. Absolute Maximum Ratings (Note)
Absolute Maximum Ratings (Note)
Absolute Maximum Ratings (Note)
Absolute Maximum Ratings (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Input diode current
Output diode current
Output current
V
CC
/ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
Note
(Note 1)
Rating
-0.5 to 7.0
-0.5 to 7.0
-0.5 to V
CC
+ 0.5
-20
±20
±25
±50
180
-65 to 150
Unit
V
V
V
mA
mA
mA
mA
mW
Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even
destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
Note 1: 180 mW in the range of T
a
= -40 to 85 . From T
a
= 85 to 125 a derating factor of -3.25 mW/ shall be
applied until 50 mW.
10.
10.
10.
10. Operating Ranges (Note)
Operating Ranges (Note)
Operating Ranges (Note)
Operating Ranges (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Operating temperature
Input rise and fall times
Symbol
V
CC
V
IN
V
OUT
T
opr
dt/dv
Test Condition
V
CC
= 3.3 ± 0.3 V
V
CC
= 5.0 ± 0.5 V
Rating
2.0 to 5.5
0 to 5.5
0 to V
CC
-40 to 125
0 to 100
0 to 20
Unit
V
V
V
ns/V
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either V
CC
or GND.
2017-02-22
Rev.5.0
©2016 Toshiba Corporation
P1-P3P4-P6P7-P9

74VHC74FT

Mfr. #:
Buy 74VHC74FT
Manufacturer:
Toshiba
Description:
Flip Flops CMOS Logic IC Series
Lifecycle:
New from this manufacturer.
Delivery:
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