MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
15
Maxim Integrated
__________ Applications Information
Power-On Reset
When power is first applied and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1204 in internal clock mode, ready to convert with
SSTRB = high. After the power supplies are stabilized,
the internal reset time is 100µs. No conversions should
be performed during this phase. SSTRB is high on
power-up, and if CS is low, the first logical 1 on DIN is
interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros.
Reference-Buffer Compensation
In addition to its shutdown function, SHDN also selects
internal or external compensation. The compensation
affects both power-up time and maximum conversion
speed. Compensated or not, the minimum clock rate is
100kHz due to droop on the sample-and-hold.
Float SHDN to select external compensation. The
Typical
Operating Circuit
uses a 4.7µF capacitor at REF. A value
of 4.7µF or greater ensures stability and allows converter
operation at the 2MHz full clock speed. External com-
pensation increases power-up time (see the section
Choosing Power-Down Mode,
and Table 5).
Internal compensation requires no external capacitor at
REF, and is selected by pulling SHDN high. Internal com-
pensation allows for the shortest power-up times, but is
only available using an external clock up to 400kHz.
Power-Down
Choosing Power-Down Mode
You can save power by placing the converter in a
low-current shutdown state between conversions.
Select full power-down or fast power-down mode via
bits 1 and 0 of the DIN control byte with SHDN high or
open (Tables 2 and 6). Pull SHDN low at any time to shut
down the converter completely. SHDN overrides bits 1
and 0 of the control byte.
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
