22
LTC4221
4221fa
supply voltages, the LTC4221 can drive any MOSFET rated
with 4.5V or 2.5V gate drive. For higher supply voltages up
to 13.5V, the LTC4221 can drive any MOSFET rated with
a 10V or 4.5V gate drive. The selected MOSFET should
fulfill two V
GS
criteria:
1. Positive V
GS
absolute maximum rating > LTC4221’s
maximum ΔV
GATE
.
2. Negative V
GS
absolute maximum rating > supply volt-
age. The gate of the MOSFET can discharge faster than
V
OUT
when shutting down the MOSFET with a large
C
LOAD
.
If one of the conditions cannot be met, an external zener
clamp shown on Figure 15 can be used. The clamp
network is connected from each channel’s GATE to the
V
OUT
pins. V
GS
is clamped in both directions and R
G
limits
the current flow into the GATE
n
pin’s internal zener clamp
during transient events.
A MOSFET with a V
GS
absolute maximum rating of ±20V
meets the two criteria for all the LTC4221 application ranges
from 1V to 13.5V. Typically most 10V gate rated MOSFETs
have V
GS
absolute maximum ratings of ±20V or greater, so
no external V
GS
zener clamp is needed. There are 4.5V gate
rated MOSFETs with V
GS
absolute maximum ratings of
±20V. In addition to the MOSFET gate drive rating and V
GS
absolute maximum rating, other criteria such as V
BDSS
,
I
D(MAX)
, R
DS(ON)
, P
D
, θ
JA
, T
J(MAX)
and maximum safe
operating area (SOA) should also be carefully reviewed.
V
BDSS
should exceed the maximum supply voltage inclu-
sive of spikes and ringing. I
D(MAX)
must exceed the maxi-
mum short-circuit current in the channel during a fault
condition. R
DS(ON)
determines the MOSFET V
DS
which to-
gether with V
RSENSE
yields an error in the V
OUT
voltage. For
example, at 1V V
CC2
, V
DS
+ V
RSENSE2
= 50mV gives a 5%
V
OUT2
error. At higher V
CC
voltages the V
DS
requirement can
be relaxed in which case the MOSFET’s thermal require-
ments (P
D
, T
J(MAX)
, SOA) may limit the value of R
DS(ON)
.
The power dissipated in the MOSFET is (I
LOAD
)
2
• R
DS(ON)
and this should be less than the maximum power dissipa-
tion, P
D
, allowed in that package. Given power dissipation,
the MOSFET junction temperature, T
J
can be computed
from the operating temperature (T
A
) and the MOSFET
package thermal resistance (θ
JA
). The operating T
J
should
be less than the T
J(MAX)
specification. The V
DS
• I
LOAD
figure must also be well within the manufacturer’s recom-
mended safe operating area (SOA) with sufficient margin.
These three thermal parameters must not be exceeded for
all conditions in a channel including normal mode opera-
tion, start-up with or without current limit, fault and
autoretry after a fault. To ensure a reliable design, fault
tests should be evaluated in the laboratory.
V
CC
Transient Protection
Good engineering practice calls for bypassing the supply
rail of any analog circuit. Bypass capacitors are often
placed at the supply connection of every active device, in
addition to one or more large value bulk bypass capacitors
per supply rail. If power is connected abruptly, the large
bypass capacitors slow the rate of rise of the supply
voltage and heavily damp any parasitic resonance of lead
or PC track inductance working against the supply bypass
capacitors.
The opposite is true for LTC4221 Hot Swap circuits
mounted on plug-in cards since controlling the surge
current to bypass capacitors at plug-in is the primary
motivation for the Hot Swap controller. In most cases,
there is no supply bypass capacitor present on the pow-
ered supply voltage side of the MOSFET switch. Although
wire harness, backplane and PCB trace inductances are
usually small, these can create large spikes when large
currents are suddenly drawn, cut off or limited. Abrupt
intervention can prevent subsequent damage caused by a
catastrophic fault but it does cause a large supply tran-
sient. These ringing transients appear as a fast edge on
APPLICATIO S I FOR ATIO
WUUU
*USER SELECTED VOLTAGE CLAMP
(A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED)
1N4688 (5V)
1N4692 (7V): LOGIC-LEVEL MOSFET
1N4695 (9V)
1N4702 (15V): STANDARD-LEVEL MOSFET
R
SENSE
GATE
4221 F15
Q1
R
G
200Ω
D1* D2*
V
CC
V
OUT
Figure 15. Gate Protection Zener Clamp
