11
LTC4221
4221fa
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient cur-
rents from the power bus as they charge. The flow of
current may damage the connector pins and glitch the
power bus, causing other boards in the system to reset.
The LTC4221 is designed to turn on and off a circuit
board’s supply voltages in a controlled manner, allowing
insertion or removal without glitches or connector dam-
age. The LTC4221 can reside on the backplane or on the
removable circuit board for hot insertion applications. It
controls the path between the backplane power bus and
the daughter board load with an external MOSFET switch.
Both inrush control and short-circuit protection are pro-
vided by the external MOSFET. Each LTC4221 controls
two channels, each with its individual MOSFET for sup-
plies from 1V to 13.5V.
Overview
The timing diagram in Figure 1 shows some typical wave-
forms of the LTC4221. The V
CC
and GND pins receive
power through the longest connector pins and are the first
to connect when the board is inserted. During the under-
voltage lockout (UVLO) state before time point 1, both
GATE pins are held low by internal N-channel MOSFET
pull-downs, turning the external MOSFETs off. Once both
V
CC
pins are valid at time point 1, the LTC4221 enters into
a reset state as ON1 is below its reset threshold. At time
point 2, ON1 clears its reset threshold and the device goes
from the reset state to an off state. When either ON1 or
ON2 clears its off threshold, both GATE pins are < 0.4V and
TIMER < 0.4V (time points 3 and 4), the TIMER pin sources
1.9μA and an initial timing cycle starts. Any transition of
ON1 and ON2 through their off thresholds will reset the
initial timing cycle. At time point 5, TIMER reaches its high
threshold and is pulled down by an internal N-channel
MOSFET to its low threshold at time point 6. The LTC4221
then checks that FILTER pin voltage is low and FAULT pin
voltage is high. If both conditions are met, the electronic
circuit breaker is armed. The channel 1 start-up timing
cycle starts at time point 6 since ON1 has cleared its off
threshold and ON2 has not.
OPERATIO
U
During the start-up cycle, TIMER sources 20μA and GATE1
sources 9.5μA. As GATE1 ramps up, MOSFET1 starts to
turn on and current flows through to charge up the load
capacitance. As V
OUT1
and FB1 ramp up, the load current
is monitored through the external SENSE1 resistor. Be-
tween time points 7 and 8, the GATE1 9.5μA pull-up is
controlled to servo the voltage across R
SENSE1
to be less
than the SENSE1 active current limit voltage, which has a
component controlled by the FB1 voltage (see Applica-
tions Information: Start-Up Cycle with Current Limit). In
this way, inrush current is limited and MOSFET1 does not
overheat during the start-up cycle. When FB1 clears its
undervoltage threshold, PWRGD1 asserts high. At time
point 9, TIMER reaches its high threshold and is pulled
down by an internal N-channel MOSFET to its low thresh-
old at time point 10. Channel 1’s slow comparator is armed
at time point 9 and enters a fault monitor mode, bringing
the channel 1 start-up cycle to an end.
At time point 10, ON2 voltage is monitored and since ON2
has cleared its off threshold, the start-up timing cycle
repeats for channel 2. The inrush current is low and GATE2
ramps up without need for current limiting. Channel 2’s
slow comparator is armed at time point 11 and enters a
fault monitor mode, ending the channel 2 start-up cycle.
Overcurrent faults translate to an increase in either V
RSENSE
.
At time point 13, V
RSENSE1
> 25mV (slow comparator
threshold). The 1.8μA pull-down on the FILTER changes to
a 105μA pull-up. When the FILTER pin hits its threshold at
time point 14, it triggers a fault state when FAULT is
latched low and both GATE pins are pulled low by internal
N-channel MOSFETs, turning off the external MOSFETs.
As each channel output discharges, its FB pin goes below
the undervoltage threshold and the PWRGD pin deasserts.
Higher overcurrents when either V
RSENSE
> 100mV (fast
comparator threshold) for more than 1μs will trigger the
same condition. This fault state can only be cleared by a
UVLO at either V
CC
pin or a hard reset at the ON1 pin, as
at time point 15, when ON1 is pulled below its reset
threshold. The LTC4221 then reverts back to its reset state
as between time points 1 and 2.
