PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 25 September 2014 7 of 32
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
7.2 Command register
Following the successful acknowledgement of the slave address + R/W bit, the bus
master will send a byte to the PCA9574, which will be stored in the Command register.
The lowest three bits are used as a pointer to determine which register will be accessed.
Only a command register code with the three least significant bits equal to the eight
allowable values as defined in Table 4 “
Register summary” will be acknowledged.
Reserved or undefined command codes will not be acknowledged. At power-up, this
register defaults to 00h, with the AI bit set to ‘0’, and the lowest 3 bits set to ‘0’.
If the Auto-Increment flag is set (AI = 1), the three least significant bits of the Command
register are automatically incremented after a read or write. This allows the user to
program and/or read the eight command registers (listed in Table 4
) sequentially. It will
then roll over to register 00h after the last register is accessed and the selected registers
will be overwritten or re-read.
If the Auto-Increment flag is cleared (AI = 0), the three least significant bits are not
incremented after data is read or written, only one register will be repeatedly read or
written.
7.3 Register definitions
7.4 Writing to port registers
Data is transmitted to the PCA9574 by sending the device address and setting the least
significant bit to logic 0 (see Figure 5
for device address). The command byte is sent after
the address and determines which register will receive the data following the command
byte. Each 8-bit register may be updated independently of the other registers.
Reset state = 00h
Remark: The Command register does not apply to Software Reset I
2
C-bus address.
Fig 6. Command register
002aad056
AI X X X X D2 D1 D0
register address
Auto-Increment flag
Table 4. Register summary
Register
number
D2 D1 D0 Name Type Function
00h 0 0 0 IN read only Input port register
01h 0 0 1 INVRT read/write Polarity inversion register
02h 0 1 0 BKEN read/write Bus-hold enable register
03h 0 1 1 PUPD read/write Pull-up/pull-down selector register
04h 1 0 0 CFG read/write Port configuration register
05h 1 0 1 OUT read/write Output port register
06h 1 1 0 MSK read/write Interrupt mask register
07h 1 1 1 INTS read only Interrupt status register
