NLV74HC374ADTR2G Datasheet MC74HC374ADWR2G, MC74HC374ADWG, MC74HC374ADTG | P4-P6

MC74HC374A

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4

TIMING REQUIREMENTS (C

L

= 50 pF, Input t

r

= t

f

= 6.0 ns)

Symbo

l

Parameter Figure

V

CC

Volts

Guaranteed Limit

Unit

–55 to 25_C v 85_C v 125_C

Min Max Min Max Min Max

t

su

Minimum Setup Time, Data to Clock 3 2.0

3.0

4.5

6.0

50

40

10

9

65

50

13

11

75

60

15

13

ns

t

h

Minimum Hold Time, Clock to Data 3 2.0

3.0

4.5

6.0

5.0

5 0

5.0

ns

t

w

Minimum Pulse Width, Clock 1 2.0

3.0

4.5

6.0

60

23

12

10

75

27

15

13

90

32

18

15

ns

t

r

, t

f

Maximum Input Rise and Fall Times 1 2.0

3.0

4.5

6.0

1000

800

500

400

1000

800

500

400

1000

800

500

400

ns

SWITCHING WAVEFORMS

Figure 1.

t

r

t

f

V

CC

GND

t

THL

t

TLH

90%

50%

10%

90%

50%

10%

CLOCK

t

PLH

t

PHL

Q

t

W

1/f

max

50%

OUTPUT

ENABLE

Q

t

PZL

t

PLZ

t

PZH

t

PHZ

10%

90%

V

CC

GND

HIGH

IMPEDANCE

V

OL

V

OH

HIGH

IMPEDANCE

50%

DATA

CLOCK

V

CC

V

CC

GND

VALID

t

h

t

su

50%

Q

Figure 2.

Figure 3.

MC74HC374A

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5

TEST CIRCUITS

Figure 4.

*Includes all probe and jig capacitance

C

L

*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

*Includes all probe and jig capacitance

C

L

*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

CONNECT TO V

CC

WHEN

TESTING t

PLZ

AND t

PZL

.

CONNECT TO GND WHEN

TESTING t

PHZ

AND t

PZH

.

1 kW

Figure 5.

Figure 6. Expanded Logic Diagram

D0

3

DQ

C

Q0

2

D1

4

DQ

C

Q1

5

D2

7

DQ

C

Q2

6

D3

8

DQ

C

Q3

9

D4

13

DQ

C

Q4

12

D5

14

DQ

C

Q5

15

D6

17

DQ

C

Q6

16

D7

18

DQ

C

Q7

19

Clock

Output

Enable

11

1

ORDERING INFORMATION

Device Package Shipping

†

MC74HC374ADWG SOIC−20 WIDE

(Pb−Free)

38 Units / Rail

NLV74HC374ADWG* SOIC−20 WIDE

(Pb−Free)

38 Units / Rail

MC74HC374ADWR2G SOIC−20 WIDE

(Pb−Free)

1000 Tape & Reel

NLV74HC374ADWR2G* SOIC−20 WIDE

(Pb−Free)

1000 Tape & Reel

MC74HC374ADTG TSSOP−20

(Pb−Free)

75 Units / Rail

MC74HC374ADTR2G TSSOP−20

(Pb−Free)

2500 Tape & Reel

NLV74HC374ADTR2G* TSSOP−20

(Pb−Free)

2500 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

MC74HC374A

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6

PACKAGE DIMENSIONS

TSSOP−20

DT SUFFIX

CASE 948E

ISSUE C

DIM

A

MIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B 4.30 4.50 0.169 0.177

C 1.20 0.047

D 0.05 0.15 0.002 0.006

F 0.50 0.75 0.020 0.030

G 0.65 BSC 0.026 BSC

H 0.27 0.37 0.011 0.015

J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION:

MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE

MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH OR GATE BURRS

SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

110

1120

PIN 1

IDENT

A

B

−T−

0.100 (0.004)

C

D

G

H

SECTION N−N

K

K1

JJ1

N

M

F

−W−

SEATING

PLANE

−V−

−U−

S

U

M

0.10 (0.004) V

S

T

20X REFK

L

L/2

2X

S

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252

--- ---

S

U0.15 (0.006) T

7.06

16X

0.36

16X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

NLV74HC374ADTR2G

NLV74HC374ADTR2G

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