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MC100EP51DTG

P1-P3P4-P6P7-P9P10-P11
© Semiconductor Components Industries, LLC, 2012
November, 2012 − Rev. 10
1 Publication Order Number:
MC10EP51/D
MC10EP51, MC100EP51
3.3V / 5V ECL D Flip-Flop
with Reset and Differential
Clock
Description
The MC10/100EP51 is a differential clock D flip−flop with reset.
The device is functionally equivalent to the EL51 and LVEL51
devices.
The reset input is an asynchronous, level triggered signal. Data
enters the master portion of the flip−flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition
of the clock. The differential clock inputs of the EP51 allow the device
to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability
under open input conditions. When left open, the CLK input will be
pulled down to V
EE
and the CLK input will be biased at V
CC
/2.
The 100 Series contains temperature compensation.
Features
• 350 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
• NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• These Devices are Pb−Free and are RoHS Compliant
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
H = MC10
K = MC100
5S = MC10
3N = MC100
M
= Date Code
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
TSSOP−8
DT SUFFIX
CASE 948R
HP51
ALYWG
G
KP51
ALYWG
G
1
8
1
8
1
8
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
DFN8
MN SUFFIX
CASE 506AA
5S MG
G
(Note: Microdot may be in either location)
HEP51
ALYW
G
1
8
KEP51
ALYW
G
1
8
1
8
1
3N MG
G
11
MC10EP51, MC100EP51
http://onsemi.com
2
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
1
2
3
45
6
7
8
Q
V
EE
V
CC
D
Q
CLK
CLK
RESET
D
R
Flip-Flop
Table 1. PIN DESCRIPTION
PIN
CLK*, CLK
*
Reset* ECL Asynchronous Reset
FUNCTION
ECL Clock Inputs
D* ECL Data Input
Q, Q
ECL Data Outputs
V
CC
Positive Supply
V
EE
Negative Supply
Table 2. TRUTH TABLE
D
L
H
X
R
L
L
H
CLK
Z
Z
X
Q
L
H
L
Z = LOW to HIGH Transition
* Pins will default LOW when left open.
EP (DFN8 only) Thermal exposed
pad must be connected to a suf-
ficient thermal conduit. Electric-
ally connect to the most negative
supply (GND) or leave uncon-
nected, floating open.
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor N/A
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg
SOIC−8
TSSOP−8
DFN8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 165 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MC10EP51, MC100EP51
http://onsemi.com
3
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 6 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −6 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
v V
CC
V
I
w V
EE
6
−6
V
V
I
out
Output Current Continuous
Surge
50
100
mA
mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 °C/W
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 °C/W
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
T
sol
Wave Solder Pb
Pb−Free
265
265
°C
q
JC
Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 5. 10EP DC CHARACTERISTICS, PECL V
CC
= 3.3 V, V
EE
= 0 V (Note 3)
Symbol
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
I
EE
Power Supply Current 26 34 44 26 35 45 28 37 47 mA
V
OH
Output HIGH Voltage (Note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV
V
OL
Output LOW Voltage (Note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV
V
IH
Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV
V
IL
Input LOW Voltage (Single−Ended) 1365 1690 1430 1755 1490 1815 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 5)
2.0 3.3 2.0 3.3 2.0 3.3 V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.3 V to −2.2 V.
4. All loading with 50 W to V
CC
− 2.0 V.
5. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
P1-P3P4-P6P7-P9P10-P11

MC100EP51DTG

Mfr. #:
Buy MC100EP51DTG
Manufacturer:
ON Semiconductor
Description:
Flip Flops 3.3V/5V ECL D-Type w/Reset and Diff Clk
Lifecycle:
New from this manufacturer.
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