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MT8812AP1

P1-P3P4-P6P7-P9P10-P10
MT8812 Data Sheet
4
Zarlink Semiconductor Inc.
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
† DC Electrical Characteristics are over recommended temperature range.
‡ Typical figures are at 25
C and are for design aid only; not guaranteed and not subject to production testing.
Absolute Maximum Ratings*- Voltages are with respect to V
SS
unless otherwise stated.
Parameter Symbol Min. Max. Units
1 Supply Voltage V
DD
V
SS
-0.3
-0.3
16.0
V
DD
+0.3
V
V
2 Analog Input Voltage V
INA
-0.3 V
DD
+0.3 V
3 Digital Input Voltage V
IN
V
SS
-0.3 V
DD
+0.3 V
4 Current on any I/O Pin I 15 mA
5 Storage Temperature T
S
-65 +150 C
6 Package Power Dissipation PLASTIC DIP P
D
0.6 W
Recommended Operating Conditions
- Voltages are with respect to V
SS
unless otherwise stated.
Characteristics Sym. Min. Typ. Max. Units Test Conditions
1 Operating Temperature T
O
025 70 C
2 Supply Voltage V
DD
4.5 14.5 V
3 Analog Input Voltage V
INA
V
SS
V
DD
V
4 Digital Input Voltage V
IN
V
SS
V
DD
V
DC Electrical Characteristics
†
- Voltages are with respect to V
SS
=0V, V
DD
=14V unless otherwise stated.
Characteristics Sym. Min. Typ.
‡
Max. Units Test Conditions
1 Quiescent Supply Current I
DD
1100A All digital inputs at V
IN
=V
SS
or
V
DD
7 15 mA All digital inputs at V
IN
=2.4V
2 Off-state Leakage Current
(See G.9 in Appendix)
I
OFF
1 500 nA IV
Xi
- V
Yj
I = V
DD
- V
SS
See Appendix, Fig. A.1
3 Input Logic “0” level V
IL
0.8 V
4 Input Logic “1” level V
IH
2.4 V
5 Input Leakage (digital pins) I
LEAK
0.1 10 A All digital inputs at V
IN
= V
SS
or V
DD
MT8812 Data Sheet
5
Zarlink Semiconductor Inc.
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
‡ Typical figures are at 25
C and are for design aid only; not guaranteed and not subject to production testing.
Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5 dB better.
DC Electrical Characteristics- Switch Resistance - V
DC
is the external DC offset applied at the analog I/O pins.
Characteristics Sym. 25C60C70C Units Test Conditions
Typ. Max. Typ. Max. Typ. Max.
1 On-state V
DD
=14V
Resistance V
DD
=12V
V
DD
=10V
V
DD
= 5V
(See G.1, G.2, G.3 in
Appendix)
R
ON
45
60
65
145
65
85
95
220
75
95
110
260
V
SS
=0V,V
DC
=V
DD
/2,
IV
Xi
-V
Yj
I = 0.4V
See Appendix, Fig. A.2
2 Difference in on-state
resistance between two
switches
(See G.4 in Appendix)
R
ON
510 10 10 V
DD
=14V, V
SS
=0,
V
DC
=V
DD
/2,
IV
Xi
-V
Yj
I = 0.4V
See Appendix, Fig. A.2
AC Electrical Characteristics
†
- Crosspoint Performance-V
DC
is the external DC offset applied at the analog
I/O pins. Voltages are with respect to V
DD
=7V, V
DC
=0V, V
SS
=-7V, unless otherwise stated.
Characteristics Sym. Min. Typ.
‡
Max. Units Test Conditions
1 Switch I/O Capacitance C
S
20 pF f=1 MHz
2 Feedthrough Capacitance C
F
0.2 pF f=1 MHz
3 Frequency Response
Channel “ON”
20LOG(V
OUT
/V
Xi
)=-3dB
F
3dB
45 MHz Switch is “ON”; V
INA
= 2Vpp
sinewave; R
L
= 1k
See Appendix, Fig. A.3
4 Total Harmonic Distortion
(See G.5, G.6 in Appendix)
THD 0.01 % Switch is “ON”; V
INA
= 2Vpp
sinewave f= 1kHz; R
L
=1k
5 Feedthrough
Channel “OFF”
Feed.=20LOG (V
OUT
/V
Xi
)
(See G.8 in Appendix)
FDT -95 dB All Switches “OFF”; V
INA
=
2Vpp sinewave f= 1kHz;
R
L
= 1k.
See Appendix, Fig. A.4
6 Crosstalk between any two
channels for switches Xi-Yi and
Xj-Yj.
Xtalk=20LOG (V
Yj
/V
Xi
).
(See G.7 in Appendix).
X
talk
-45 dB V
INA
=2Vpp sinewave
f= 10MHz; R
L
= 75
-90 dB V
INA
=2Vpp sinewave
f= 10kHz; R
L
= 600
-85 dB V
INA
=2Vpp sinewave
f= 10kHz; R
L
= 1k
-80 dB V
INA
=2Vpp sinewave
f= 1kHz; R
L
= 10k
Refer to Appendix, Fig. A.5
for test circuit.
7 Propagation delay through
switch
t
PS
30 ns R
L
=1k; C
L
=50pF
MT8812 Data Sheet
6
Zarlink Semiconductor Inc.
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5ns.
‡ Typical figures are at 25
C and are for design aid only; not guaranteed and not subject to production testing.
Refer to Appendix, Fig. A.7 for test circuit.
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
AC Electrical Characteristics
†
- Control and I/O Timings- V
DC
is the external DC offset applied at the analog
I/O pins. Voltages are with respect to V
DD
=7V, V
DC
=0V, V
SS
=-7V, unless otherwise stated.
Characteristics Sym. Min. Typ.
‡
Max. Units Test Conditions
1 Control Input crosstalk to switch
(for CS, DATA, STROBE,
Address)
CX
talk
30 mVpp V
IN
=3V+V
DC
squarewave;
R
IN
=1k, R
L
=10k.
See Appendix, Fig. A.6
2 Digital Input Capacitance C
DI
10 pF f=1MHz
3 Switching Frequency F
O
20 MHz
4 Setup Time DATA to STROBE t
DS
10 ns R
L
= 1k, C
L
=50pF
5 Hold Time DATA to STROBE t
DH
10 ns R
L
= 1k, C
L
=50pF
6 Setup Time Address to STROBE t
AS
10 ns R
L
= 1k, C
L
=50pF
7 Hold Time Address to STROBE t
AH
10 ns R
L
= 1k, C
L
=50pF
8 STROBE Pulse Width t
SPW
20 ns R
L
= 1k, C
L
=50pF
9 RESET Pulse Width t
RPW
40 ns R
L
= 1k, C
L
=50pF
10 STROBE to Switch Status Delay t
S
40 100 ns R
L
= 1k, C
L
=50pF
11 DATA to Switch Status Delay t
D
50 100 ns R
L
= 1k, C
L
=50pF
12 RESET to Switch Status Delay t
R
35 100 ns R
L
= 1k, C
L
=50pF
t
RPW
t
SPW
t
AS
t
AH
t
DH
t
D
t
S
t
R
t
R
t
DS
50% 50%
50%50%50%
50% 50%
50% 50%
RESET
STROBE
ADDRESS
DATA
SWITCH*
ON
OFF
P1-P3P4-P6P7-P9P10-P10

MT8812AP1

Mfr. #:
Buy MT8812AP1
Manufacturer:
Microchip / Microsemi
Description:
Analog & Digital Crosspoint ICs Pb Free 8x12 ANALOG SWITCH PLCC
Lifecycle:
New from this manufacturer.
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