Data Sheet HMC1055
Rev. A | Page 9 of 10
APPLICATIONS INFORMATION
EVALUATION PRINTED CIRCUIT BOARD (PCB)
The HMC1055 evaluation board is constructed of a 4-layer
material with a copper thickness of 0.7 mil on each layer. Every
copper layer is separated with a dielectric material. The top
dielectric material is 10 mil RO4350. The middle and bottom
dielectric materials are FR-4, used for mechanical strength and
overall board thickness of approximately 62 mil, which allows
SMA connectors to be slipped in at the board edges.
All RF and dc traces are routed on the top copper layer. The RF
transmission lines are designed using a coplanar waveguide
(CPWG) model, with a width of 16 mil, spacing of 13 mil, and
dielectric thickness of 10 mil, to have a characteristic imped-
ance of 50 Ω. The inner and bottom layers are grounded planes
to provide a solid ground for the RF transmission lines. For
optimal electrical and thermal performance, as many vias as
possible are arranged around the transmission lines and under
the package exposed pad. The evaluation board layout shown in
Figure 14 serves as a recommendation for optimal and stable
performance, as well as for improvement of thermal efficiency.
The package ground pins are connected directly to the ground
plane. The supply voltage and control voltage must be con-
nected to the dc pins, J3 and J4, respectively, of the evaluation
board. One decoupling capacitor is populated on the supply
trace to filter high frequency noise.
The RF input and output ports (RF1 and RF2) are connected
through 50 transmission lines to the SMA connectors, J1
and J2, respectively. The RF1 and RF2 ports are ac-coupled
with capacitors of an appropriate value to ensure broadband
performance. A thru calibration line connects J5 and J6; this
transmission line is used to estimate the loss of the PCB over
the environmental conditions being evaluated.
EVALUATION BOARD SCHEMATIC AND ARTWORK
Figure 13. Evaluation Board Schematic
Table 5. List of Materials for EVAL01-HMC1055LP2C
Item Description
J1, J2 PCB mount, SMA, RF connector
J3, J4 DC pin
C1 1 nF capacitor, 0402 package
C2, C3 330 pF capacitor, 0402 package
U1 HMC1055 SPST switch
PCB 600-00215-00-1 evaluation PCB
Figure 14. Evaluation Board Layout—Top View
13718-013
J6
DEPOP
1
J5
DEPOP
1
C4
330pF
DEPOP
C5
330pF
DEPOP
U1
HMC1055
8
7
6
1
3
4
5
2
NIC
GND
GND
NIC
RF2
V
CTL
V
DD
RF1
J2
RF2
1
C3
330pF
J4J3
J1
RF1
1
C2
330pF
C1
1nF
13718-014
