MC74VHC126
Quad Bus Buffer
with 3−State Control Inputs
The MC74VHC126 is a high speed CMOS quad bus buffer
fabricated with silicon gate CMOS technology. It achieves
noninverting high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining CMOS low power dissipation.
The MC74VHC126 requires the 3−state control input (OE) to be set
Low to place the output into high impedance.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
• High Speed: t
PD
= 3.8 ns (Typ) at V
CC
= 5.0 V
• Low Power Dissipation: I
CC
= 4.0 μA (Max) at T
A
= 25°C
• High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 5
1 Publication Order Number:
MC74VHC126/D
14−LEAD SOIC
D SUFFIX
CASE 751A
14−LEAD TSSOP
DT SUFFIX
CASE 948G
PIN CONNECTIONS
Device Package Shipping
ORDERING INFORMATION
MC74VHC126DR2G SOIC 2500 Units/Reel
MC74VHC126DTR2G TSSOP
2500 Units/Reel
11
12
13
14
8
9
105
4
3
2
1
7
6
OE3
Y4
A4
OE4
V
CC
Y3
A3
OE2
Y1
A1
OE1
GND
Y2
A2
http://onsemi.com
See general marking information in the device marking
section on page 7 of this data sheet.
DEVICE MARKING INFORMATION
(Top View)
