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LX5261CDP

P1-P3P4-P6
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 1
Copyright © 2000
Rev. 1.0c, 2005-02-08
WWW.Microsemi .COM
LX5261
27-Line LVD SCSI Source/Sink Re
g
ulator
P
R
ODUCTION
D
ATA
S
HEET
TM
®
DESCRIPTION
The LX5261 is a source/sink
regulator designed to provide the
correct reference voltages and bias
currents for SCSI LVD applications.
With the proper LVD termination
network (475Ω, 121Ω, 475Ω), the
LX5261 assures that LVD performance
is compliant to the SPI-2 (Ultra2), SPI-
3 (Ultra160) and SPI-4 (Ultra320)
specification.
The LX5261 provides two fixed
regulated outputs (1.75V and 0.75V)
each capable of sourcing / sinking
200mA, along with a buffered 1.3V
output for DIFSENS signaling.
The LX5261 features on-chip
trimming of the internal voltage enabling
precise output voltages; typically +/- 1%
of its specified value. Thermal Shutdown
and Current Limiting is integrated on-
chip.
The LX5261 is available in the 16-
pin SOIC (DP) package.
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
KEY FEATURES
Compliant with SPI-2 (Ultra2),
SPI-3 (Ultra160), and SPI-4
(Ultra320)
2.7V to 5.25V Operation
200mA Source/Sink Capability
DIFSENS Line Driver
Current Limit and Thermal
Protection
Pin Compatible With Unitrode
UCC561
TYPICAL APPLICATION
PACKAGE ORDER INFO
DP
SOIC
16-Pin
T
A
(°C)
RoHS Compliant / Pb-free
Transition DC: 0440
0 to 70
LX5261CDP
Note: Available in Tape & Reel.
Append the letters “TR” to the part number. (i.e. LX5261CDP-TR)
L
L
X
X
5
5
2
2
6
6
1
1
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 2
Copyright © 2000
Rev. 1.0c, 2005-02-08
WWW.Microsemi .COM
LX5261
27-Line LVD SCSI Source/Sink Re
g
ulator
P
R
ODUCTION
D
ATA
S
HEET
TM
®
ABSOLUTE MAXIMUM RATINGS
Term Power (VTERM) .........................................................................................................6V
Operating Junction Temperature..................................................................................... 150°C
Storage Temperature Range..............................................................................-65°C to 150°C
RoHS / Pb-freePeak Package Solder Reflow Temperature
(40 second maximum exposure) ........................................................................ 260°C (+0, -5)
Note:
Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground.
Currents are positive into, negative out of specified terminal.
THERMAL DATA
DP
16-Pin SOIC
T
HERMAL
R
ESISTANCE
-J
UNCTION TO
A
MBIENT
,
θ
JA
111.8 °C/W
Junction Temperature Calculation: T
J
= T
A
+ (P
D
x θ
JA
).
The θ
JA
numbers are guidelines for the thermal performance of the device/pc-board
system. All of the above assume no ambient airflow. θ
JA
can vary significantly
depending on mounting technique. (See Application Notes Section: Thermal
considerations)
PACKAGE PIN OUT
2
3
5
4
15
14
11
12
6
7
10
8
N/C
9
116N/C
N/C
N/C
N/C
N/C
N/C
N/C
VOUT1
VOUT2
VTERM
HSGND
HSGNDHSGND
GND
DIFSENS
13
DP
P
ACKAGE
(Top View)
NC – No Internal Connection
RoHS / Pb-free 100% Matte Tin Lead
Finish
FUNCTIONAL PIN DESCRIPTION
P
IN
N
AME
D
ESCRIPTION
VOUT1
1.75V Regulated Output. Capable of sourcing/sinking 200mA.
VOUT2
0.75V Regulated Output. Capable of sourcing/sinking 200mA.
VTERM
Power supply pin for terminator. Connect to SCSI bus VTERM. Usually decoupled
by one 4.7
µ
F low-ESR capacitor. It is absolutely necessary to connect this pin to the
decoupling capacitor through a very low impedance (big traces to PCB). Keeping distances
very short from the decoupling capacitors is somewhat layout dependent and some
applications may benefit from high frequency decoupling with 0.1
µ
F capacitors at VTERM
pin.
DIFSENS 1.3V buffered output for DIFSENS signaling.
GND
Regulator ground pin. Connect to ground.
HSGND
Attached to die mounting pad, but not bonded to GND pin. Pins should be considered a
heat sink only, and not a true ground connection. It is recommended that these pins be
connected to ground, but can be left floating.
P
P
A
A
C
C
K
K
A
A
G
G
E
E
D
D
A
A
T
T
A
A
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 3
Copyright © 2000
Rev. 1.0c, 2005-02-08
WWW.Microsemi .COM
LX5261
27-Line LVD SCSI Source/Sink Re
g
ulator
P
R
ODUCTION
D
ATA
S
HEET
TM
®
RECOMMENDED MAX OPERATING CONDITIONS
LX5261
Parameter Symbol
Min Typ Max
Units
VTERM V
TERM
2.7 5.25 V
Signal Line Voltage 0 5.0 V
Operating Junction Temperature T
J
0 70
°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C
≤
T
A
≤
70°C, and V
TERM
=
3.3V.
LX5261
Parameter Symbol Test Conditions
Min Typ Max
Units
`
TERMPWR Section
VTERM Supply Current I
TERM
No Load 35 40 mA
VTERM Voltage V
TERM
2.7 5.25 V
`
Regulator Section
1.75V Regulator V
REG1
-125mA < I
OUT
< 125mA, 2.7V < V
IN
< 5.25V 1.7 1.75 1.8 V
1.3V Regulator V
DIFS
DIFSENS; No Load 1.2 1.3 1.4 V
0.75V Regulator V
REG2
-125mA < I
OUT
< 125mA, 2.7V < V
IN
< 5.25V 0.7 0.75 0.8 V
1.75V Regulator Source Current I
SRC1
V
OUT
= 1.25V -200 mA
1.75V Regulator Sink Current I
SNK1
V
OUT
= 2.25V 200 mA
1.75V Source Current Limit
-700 mA
1.75V Sink Current Limit 700 mA
1.3V Regulator Source Current I
DIFS_SRC
DIFSENS; 0V -5 -15 mA
1.3V Regulator Sink Current I
DIFS_SNK
DIFSENS = 2.4V 50 200 µA
0.75V Regulator Source Current I
SRC2
V
OUT
= 0.25V -200 mA
0.75V Regulator Sink Current I
SNK2
V
OUT
= 1.25V 200 mA
0.75V Source Current Limit
-700 mA
0.75V Sink Current Limit 700 mA
E
E
L
L
E
E
C
C
T
T
R
R
I
I
C
C
A
A
L
L
S
S
P1-P3P4-P6

LX5261CDP

Mfr. #:
Buy LX5261CDP
Manufacturer:
Microchip / Microsemi
Description:
Voltage References
Lifecycle:
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