10
FN6409.0
December 18, 2006
Typical Performance Curves T
A
= +25°C, Unless Otherwise Specified
FIGURE 8. THD+N vs SUPPLY VOLTAGE vs FREQUENCY
FIGURE 9. THD+N vs SIGNAL LEVELS vs FREQUENCY
FIGURE 10. THD+N vs OUTPUT VOLTAGE FIGURE 11. THD+N vs OUTPUT POWER
THD+N (%)
FREQUENCY (Hz)
20 200 2k 20k
0.04
0.05
0.06
0.07
0.08
0.09
0.1
0.11
V
DD
= 2.6V
V
DD
= 2.7V
V
DD
= 3.6V
V
DD
= 3V
R
LOAD
= 32
V
LOAD
= 0.707V
RMS
THD+N (%)
FREQUENCY (Hz)
20 200 2k 20k
R
LOAD
= 32
V
DD
= 3V
0
0.1
0.2
0.3
0.4
2V
P-P
1V
P-P
3V
P-P
2.5V
P-P
THD+N (%)
OUTPUT VOLTAGE (V
P-P
)
00.511.522.533.5
0
0.1
0.2
0.3
0.4
0.5
R
LOAD
= 32
FREQ
= 1kHz
V
DD
=3V
THD+N (%)
OUTPUT POWER (mW)
0 1020304050
0
0.1
0.2
0.3
0.4
0.5
R
LOAD
= 32
FREQ
= 1kHz
V
DD
=3V
ISL54206
11
FN6409.0
December 18, 2006
FIGURE 12. EYE PATTERN: 480Mbps WITH SWITCH IN THE SIGNAL PATH
FIGURE 13. FREQUENCY RESPONSE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND (TDFN Paddle Connection: Tie to GND or Float)
TRANSISTOR COUNT:
98
PROCESS:
Submicron CMOS
Typical Performance Curves T
A
= +25°C, Unless Otherwise Specified (Continued)
FREQUENCY (Hz)
0
-1
NORMALIZED GAIN (dB)
1M 10M 100M 1G
V
IN
= 0.2V
P-P
to 2V
P-P
R
L
= 50
-2
-3
-4
1
USB SWITCH
ISL54206
12
FN6409.0
December 18, 2006
ISL54206
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
6
B
E
A
D
0.10 C
2X
2
0.10 M C A B
0.05 M C
(ND-1) X e
C
0.05 C
A
0.10 C
A1
SEATING PLANE
e
INDEX AREA
PIN #1 ID
3
5
(DATUM A)
(DATUM B)
N-1
1
N
NX L
NX b
21
N
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NX (b)
SECTION "C-C"
FOR ODD TERMINAL/SIDE
e
CC
5
C
L
TERMINAL TIP
(A1)
L
DETAIL “A” PIN 1 ID
L
0.05 MIN
0.10 MIN
0.10 C
2X
4xk
b
L10.2.1x1.6A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.45 0.50 0.55 -
A1 - - 0.05 -
A3 0.127 REF -
b 0.15 0.20 0.25 5
D 2.05 2.10 2.15 -
E 1.55 1.60 1.65 -
e 0.50 BSC -
k0.20
---
L 0.35 0.40 0.45 -
N102
Nd 4 3
Ne 1 3
0-12
4
Rev. 3 6/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. Same as JEDEC MO-255UABD except:
No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm
"L" MAX dimension = 0.45 not 0.42mm.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
2.00
0.80
1.75
0.25
0.50
0.275
2.50
LAND PATTERN
10

ISL54206IRUZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
USB Switch ICs AUD/USB 2 0 HI SPD SWITCH 10LD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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