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MC74HC540ADWG

P1-P3P4-P6P7-P7
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 11
1 Publication Order Number:
MC74HC540A/D
MC74HC540A
Octal 3-State Inverting
Buffer/Line Driver/Line
Receiver
High−Performance Silicon−Gate CMOS
The MC74HC540A is identical in pinout to the LS540. The device
inputs are compatible with Standard CMOS outputs. External pull−up
resistors make them compatible with LSTTL outputs.
The HC540A is an octal inverting buffer/line driver/line receiver
designed to be used with 3−state memory address drivers, clock
drivers, and other bus−oriented systems. This device features inputs
and outputs on opposite sides of the package and two ANDed
active−low output enables.
The HC540A is similar in function to the HC541A, which has
noninverting outputs.
Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7 A Requirements
• Chip Complexity: 124 FETs or 31 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Figure 1. Logic Diagram
18
Y1
2
A1
17
Y2
3
A2
16
Y3
4
A3
15
Y4
5
A4
14
Y5
6
A5
13
Y6
7
A6
12
Y7
8
A7
11
Y8
9
A8
OE1
OE2
1
19
Output
Enables
Data
Inputs
Inverting
Outputs
PIN 20 = V
CC
PIN 10 = GND
http://onsemi.com
1
20
MARKING DIAGRAMS
SOIC−20
DW SUFFIX
CASE 751D
74HC540A
AWLYYWWG
HC
540A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
20
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
SOIC−20 TSSOP−20
1920 18 17 16 15 14
21 34567
V
CC
13
8
12
9
11
10
OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND
PIN ASSIGNMENT
20−Lead (Top View)
L
L
H
X
L
L
X
H
L
H
X
X
FUNCTION TABLE
Inputs
Output Y
OE1 OE2 A
H
L
Z
Z
Z = High Impedance
X = Don’t Care
MC74HC540A
http://onsemi.com
2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage −0.5 to +7.0 V
V
I
DC Input Voltage −0.5 to V
CC
+ 0.5 V
V
O
DC Output Voltage (Note 1) −0.5 ≤ V
O
≤ V
CC
+ 0.5 V
I
IK
DC Input Diode Current ±20 mA
I
OK
DC Output Diode Current ±35 mA
I
O
DC Output Sink Current ±35 mA
I
CC
DC Supply Current per Supply Pin ±75 mA
I
GND
DC Ground Current per Ground Pin ±75 mA
T
STG
Storage Temperature Range −65 to +150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 260
_C
T
J
Junction Temperature Under Bias +150
_C
q
JA
Thermal Resistance SOIC
TSSOP
96
128
_C/W
P
D
Power Dissipation in Still Air at 85_C SOIC
TSSOP
500
450
mW
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 30% − 35% UL 94 V0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 2000
> 200
> 1000
V
I
LATCHUP
Latchup Performance Above V
CC
and Below GND at 85_C (Note 5)
±300 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
O
absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types −55 +125
_C
t
r
, t
f
Input Rise and Fall Time (Figure 3) V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
MC74HC540A
http://onsemi.com
3
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
V
Guaranteed Limit
Symbol Parameter Condition
−55 to
25°C
≤85°C ≤125°C Unit
V
IH
Minimum High−Level Input Voltage V
out
= 0.1 V
|I
out
| ≤ 20 mA
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
V
IL
Maximum Low−Level Input Voltage V
out
= V
CC
− 0.1 V
|I
out
| ≤ 20 mA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IL
|I
out
| ≤ 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
= V
IL
|I
out
| ≤ 3.6 mA
|I
out
| ≤ 6.0 mA
|I
out
| ≤ 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
|I
out
| ≤ 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
|I
out
| ≤ 3.6 mA
|I
out
| ≤ 6.0 mA
|I
out
| ≤ 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 6.0 ±0.1 ±1.0 ±1.0
mA
I
OZ
Maximum Three−State Leakage
Current
Output in High Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
6.0 ±0.5 ±5.0 ±10.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0 mA
6.0 4 40 160
mA
AC CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
V
CC
V
Guaranteed Limit
Symbol Parameter
−55 to
25°C
≤85°C ≤125°C Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
80
30
18
15
100
40
23
20
120
55
28
25
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 5)
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 5)
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 2 and 4)
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
C
in
Maximum Input Capacitance 10 10 10 pF
C
out
Maximum 3−State Output Capacitance (Output in High Impedance State) 15 15 15 pF
C
PD
Power Dissipation Capacitance (Per Buffer) (Note 7)
Typical @ 25°C, V
CC
= 5.0 V, V
EE
= 0 V
pF
35
7. Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.
P1-P3P4-P6P7-P7

MC74HC540ADWG

Mfr. #:
Buy MC74HC540ADWG
Manufacturer:
ON Semiconductor
Description:
Buffers & Line Drivers 2-6V Octal 3-State Inverting
Lifecycle:
New from this manufacturer.
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