[AK5357]
MS0294-E-03
2009/03
- 11 -
OPERATION OVERVIEW
■ System Clock
MCLK (256fs/384fs/512fs), SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be
synchronized with MCLK, however the phase is not critical.
Table 1 shows the relationship of typical sampling frequency
and the system clock frequency. MCLK frequency, SCLK frequency, HPF (ON or OFF), the input level (CMOS or TTL)
and master/slave are selected by CKS2-0 pins as shown in
Table 2.
All external clocks (MCLK, SCLK and LRCK) must be present unless the PDN pin = “L”. If these clocks are not
provided, the AK5357 may draw excess current due to its use of internal dynamically refreshed logic. If the external
clocks are not present, place the AK5357 in power-down mode (PDN pin = “L”). In master mode, the master clock
(MCLK) must be provided unless the PDN pin = “L”.
MCLK
fs
256fs 384fs 512fs 768fs
32kHz 8.192MHz 12.288MHz 16.384MHz 24.576MHz
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
48kHz 12.288MHz 18.432MHz 24.576MHz 36.864MHz
96kHz 24.576MHz 36.864MHz N/A N/A
Table 1. System Clock Example (N/A: Not available)
CKS2 CKS1 CKS0 Input Level HPF Master/Slave MCLK SCLK
L L L CMOS ON Slave
256/384fs (∼ 96kHz)
512/768fs (∼ 48kHz)
≥ 48fs or 32fs
L L H CMOS OFF Slave
256/384fs (∼ 96kHz)
512/768fs (∼ 48kHz)
≥ 48fs or 32fs
L H L CMOS ON Master
256fs (∼ 96kHz)
64fs
L H H CMOS ON Master
512fs (∼ 48kHz)
64fs
H L L TTL ON Slave
256/384fs (∼ 96kHz)
512/768fs (∼ 48kHz)
≥ 48fs or 32fs
H L H Reserved
H H L CMOS ON Master
384fs (∼ 96kHz)
64fs
H H H CMOS ON Master
768fs (∼ 48kHz)
64fs
Table 2. Mode Select
Note: SDTO outputs 16bit data at SCLK=32fs.
■ Audio Interface Format
Two kinds of data formats can be chosen with the DIF pin (
Table 3). In both modes, the serial data is in MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of SCLK. The audio interface supports both master and
slave modes. In master mode, SCLK and LRCK are output with the SCLK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode DIF pin SDTO LRCK SCLK Figure
0 L 24bit, MSB justified H/L
≥ 48fs or 32fs
Figure 1
1 H 24bit, I
2
S Compatible L/H
≥ 48fs or 32fs
Figure 2
Table 3. Audio Interface Format
