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LTC3547BEDDB-1#TRMPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
LTC3547B
10
3547bfb
APPLICATIO S I FOR ATIO
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U
Setting the Output Voltage
The LTC3547B regulates the V
FB1
and V
FB2
pins to 0.6V
during regulation. Thus, the output voltage is set by a
resistive divider according to the following formula:
V
OUT
= 0.6V 1+
R2
R
1
(4)
Keeping the current small (<5μA) in these resistors maxi-
mizes effi ciency, but making it too small may allow stray
capacitance to cause noise problems or reduce the phase
margin of the error amp loop.
To improve the frequency response of the main control
loop, a feedback capacitor (C
F
) may also be used. Great
care should be taken to route the V
FB
line away from noise
sources, such as the inductor or the SW line.
Fixed output versions of the LTC3547B (e.g. LTC3547B-1)
include an internal resistive divider, eliminating the need
for external resistors. The resistor divider is chosen such
that the V
FB
input current is 3μA. For these versions, the
V
FB
pin should be connected directly to V
OUT
. Table 2 lists
the fi xed output voltages available for the LTC3547B.
Table 2. Fixed Output Voltage Versions
Part Number V
OUT1
V
OUT2
LTC3547B Adjustable Adjustable
LTC3547B-1 1.8V 1.2V
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
• ESR, where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or dis-
charge C
OUT
generating a feedback error signal used by the
regulator to return V
OUT
to its steady-state value. During
this recovery time, V
OUT
can be monitored for overshoot
or ringing that would indicate a stability problem.
The initial output voltage step may not be within the band-
width of the feedback loop, so the standard second-order
overshoot/DC ratio cannot be used to determine the phase
margin. In addition, feedback capacitors (C
F1
and C
F2
)
can be added to improve the high frequency response, as
shown in Figure 1. Capacitor C
F
provides phase lead by
creating a high frequency zero with R2 which improves
the phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a re-
view of control loop theory, refer to Application Note 76.
In some applications, a more severe transient can be
caused by switching in loads with large (>1μF) input ca-
pacitors. The discharged input capacitors are effectively
put in parallel with C
OUT
, causing a rapid drop in V
OUT
.
No regulator can deliver enough current to prevent this
problem if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A Hot Swap
™
controller
is designed specifi cally for this purpose and usually in-
corporates current limiting, short-circuit protection, and
soft-starting.
Hot Swap is a trademark of Linear Technology Corporation.
LTC3547B
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Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Percent effi ciency can
be expressed as:
% Effi ciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four sources usually account for the losses in
LTC3547B circuits: 1) V
IN
quiescent current, 2) switching
losses, 3) I
2
R losses, 4) other system losses.
1) The V
IN
current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET
driver and control currents. V
IN
current results in a
small (<0.1%) loss that increases with V
IN
, even at
no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is a current out
of V
IN
that is typically much larger than the DC bias cur-
rent. In continuous mode, I
GATECHG
= f
O
(Q
T
+ Q
B
), where
Q
T
and Q
B
are the gate charges of the internal top and
bottom MOSFET switches. The gate charge losses are
proportional to V
IN
and thus their effects will be more
pronounced at higher supply voltages.
3) I
2
R losses are calculated from the DC resistances
of the internal switches, R
SW
, and external inductor,
R
L
. In continuous mode, the average output current
fl ows through inductor L, but is “chopped” between
the internal top and bottom switches. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
) • (DC) + (R
DS(ON)BOT
) • (1– DC)
(5)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics curves. Thus, to obtain I
2
R losses:
I
2
R losses = I
OUT
2
• (R
SW
+ R
L
)
4) Other “hidden” losses, such as copper trace and in-
ternal battery resistances, can account for additional
effi ciency degradations in portable systems. It is very
important to include these “system” level losses in
the design of a system. The internal battery and fuse
resistance losses can be minimized by making sure that
C
IN
has adequate charge storage and very low ESR at
the switching frequency. Other losses, including diode
conduction losses during dead-time, and inductor
core losses, generally account for less than 2% total
additional loss.
LTC3547B
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Thermal Considerations
In a majority of applications, the LTC3547B does not dis-
sipate much heat due to its high effi ciency. In the unlikely
event that the junction temperature somehow reaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
The goal of the following thermal analysis is to determine
whether the power dissipated causes enough temperature
rise to exceed the maximum junction temperature (125°C)
of the part. The temperature rise is given by:
T
RISE
= P
D
• θ
JA
(6)
Where P
D
is the power dissipated by the regulator and
θ
JA
is the thermal resistance from the junction of the die
to the ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
RISE
+ T
AMBIENT
(7)
As a worst-case example, consider the case when the
LTC3547B is in dropout on both channels at an input
voltage of 2.7V with a load current of 300mA and an ambi-
ent temperature of 70°C. From the Typical Performance
Characteristics graph of Switch Resistance, the R
DS(ON)
of the main switch is 0.9Ω. Therefore, power dissipated
by each channel is:
P
D
= I
OUT
2
• R
DS(ON)
= 81mV
Given that the thermal resistance of a properly soldered
DFN package is approximately 76°C/W, the junction
temperature of an LTC3547B device operating in a 70°C
ambient temperature is approximately:
T
J
= (2 • 0.081W • 76°C/W) + 70°C = 82.3°C
which is well below the absolute maximum junction tem-
perature of 125°C.
PC Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3547B. These items are also illustrated graphically
in the layout diagrams of Figures 2 and 3. Check the fol-
lowing in your layout:
1. Does the capacitor C
IN
connect to the power V
IN
(Pin 3)
and GND (Pin 5) as closely as possible? This capacitor
provides the AC current of the internal power MOSFETs
and their drivers.
2. Are the respective C
OUT
and L closely connected?
The (–) plate of C
OUT
returns current to GND and the
(–) plate of C
IN
.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C
OUT1
and a ground sense line
terminated near GND (Pin 5). The feedback signals V
FB1
and V
FB2
should be routed away from noisy components
and traces, such as the SW lines (Pins 4 and 6), and
their trace length should be minimized.
4. Keep sensitive components away from the SW pins if
possible. The input capacitor C
IN
and the resistors R1,
R2, R3 and R4 should be routed away from the SW
traces and the inductors.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at a single
point. These ground traces should not share the high
current path of C
IN
or C
OUT
.
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. These copper areas should be
connected to V
IN
or GND.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LTC3547BEDDB-1#TRMPBF

Mfr. #:
Buy LTC3547BEDDB-1#TRMPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual Monolithic 300mA Synch Step-Down Reg with fixed 1.2V & 1.8V outputs
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