STHDLS101A Functional description
Doc ID 15756 Rev 1 11/24
4 Functional description
The section describes the basic functionality of the STHDLS101A device.
Power supply
The STHDLS101A is powered by a single DC power supply of 3.3 V ± 10%.
Clocking
This device does not retime any data. The device contains no state machines. No inputs or
outputs of the device are latched or clocked.
Reset
This device acts as a level shifter, reset is not required.
OE_N function
When OE_N is asserted (low level), the IN_D and OUT_D signals are fully functional. Input
termina-tion resistors are enabled and any internal bias circuits are turned on.
OE_N pin has an internal pull-down that enables the chip if left unconnected.
When OE_N is de-asserted (high level), the OUT_D outputs are in high impedance state.
The IN_D input buffers are disabled and the IN_D termination resistors are disabled.
Internal bias circuits for the differential inputs and outputs are turned off. Power consumption
of the chip is minimized.
The HPD_SINK input and HPD_SOURCE output are not affected by OE_N. The SCL and
SDA pass-gates are not affected by OE_N.
Table 3. OE_N description
OE_N Device state Comments
Asserted (low level)
or unconnected
Differential input buffers and
output buffers enabled. Input
impedance = 50Ù
Normal functioning state for IN_D
to OUT_D level shifting function.
De-asserted (high level)
Low-power state.
Differential input buffers and
terminations are disabled.
Differential input buffers are in
high-impedance state.
OUT_D level shifting outputs are
disabled. OUT_D level shifting
outputs are in a high-impedance
state.
Internal bias currents are turned
off.
Intended for lowest power
condition when:
• No display is plugged in or
• The level shifted data path is
disabled
HPD_SINK input and
HPD_SOURCE output are not
affected by OE_N.
SCL_SOURCE, SCL_SINK,
SDA_SOURCE and SDA_SINK
signals and functions are not
affected by OE_N.
