DS2480B
16 of 31
1-WIRE COMMUNICATION WAVEFORMS
One of the major features of the DS2480B is that it relieves the host from generating the timing of the
1-Wire signals and sampling the 1-Wire bus at the appropriate times. How this is done for the
reset/presence detect sequence is shown in Figure 6a. This sequence is composed of four timing
segments: the reset low time t
RSTL
, the short/interrupt sampling offset t
SI
, the presence detect sampling
offset t
PDT
and a delay time t
FILL
. The timing segments t
SI
, t
PDT
and t
FILL
comprise the reset high time t
RSTH
where 1-Wire slave devices assert their presence or interrupt pulse. During this time the DS2480B pulls
the 1-Wire bus high with its weak pullup current.
The values of all timing segments for all 1-Wire speed options are shown in the table. Since the
reset/presence sequence is slow compared to the time slots, the values for regular and flexible speed are
the same. Except for the falling edge of the presence pulse all edges are controlled by the DS2480B. The
shape of the uncontrolled falling edge is determined by the capacitance of the 1-Wire bus and the number,
speed and sink capability of the slave devices connected.
Figure 6a. RESET/PRESENCE DETECT
Speed t
RSTL
t
SI
t
PDT
t
FILL
t
RSTH
Regular 512µs 8µs 64µs 512µs 584µs
Overdrive 64µs 2µs 8µs 64µs 74µs
Flexible 512µs 8µs 64µs 512µs 584µs
After having received the command code for generating a reset/presence sequence, the DS2480B pulls
the 1-Wire bus low for t
RSTL
and then lets it go back to 5V. The DS2480B will now wait for the
short/interrupt sampling offset t
SI
to expire and then test the voltage on the 1-Wire bus to determine if
there is a short or an interrupt signal. If there is no short or interrupt (as shown in the picture), the
DS2480B will wait for t
PDT
and test the voltage on the 1-Wire bus for a presence pulse. Regardless of the
result of the presence test, the DS2480B will then wait for t
FILL
to expire and then send the command
response byte to the host.
If the test for interrupt or short reveals a logic 0, the DS2480B will wait for 4096ms and then test the
1-Wire bus again. If a logic 0 is detected, the 1-Wire bus is shorted and a command response byte with
the code for SHORT will be sent immediately. If a logic 1 is detected, the device will wait for t
FILL
to
expire, after which it will send the command response byte with the code for an alarming presence pulse.
No additional testing for a presence pulse will be done. The DS2480B will perform the short/interrupt
testing as described also at Overdrive speed, although interrupt signaling is only defined for regular
speed.
The idle time following the Reset/Presence Detect sequence depends on the serial communication speed
and the host’s response time.
DS2480B
17 of 31
A Write-1 and Read Data time slot is comprised of the segments t
LOW1
, t
DSO
and t
HIGH
. During Write-1
time slots, after the Write-1 low time t
LOW1
is over, the DS2480B waits for the duration of the data sample
offset and then samples the voltage at the 1-Wire bus to read the response. After this, the waiting time
t
HIGH1
must expire before the time slot is complete. A Write-0 time slot only consists of the two segments
t
LOW0
and t
REC0
.
If the network is large or heavily loaded, one should select flexible speed and extend t
LOW1
to more than
8ms to allow the 1-Wire bus to completely discharge. Since a large or heavily loaded network needs more
time to recharge, it is also recommended to delay sampling the bus for reading. A higher value for t
DSO
will increase the voltage margin and also provide extra energy to the slave devices when generating a
long series of write 0 time slots. However, the total of t
LOW1
+ t
DSO
should not exceed 22ms*. Otherwise
the slave device responding may have stopped pulling the bus low when transmitting a logic 0.
The idle time between time slots within a byte or during a 12-bit sequence while the Search Accelerator is
on is 0. Between bytes, 12-bit search sequences and single bits the idle time depends on the RS232 data
rate and the host’s response time. The response byte is sent to the host as soon as the last time slot of a
byte, 12-bit sequence or the command is completed.
Figure 6b. WRITE-1 AND READ DATA TIME SLOT
Speed t
LOW1
t
DSO
t
HIGH1
t
SLOT
*
Regular 8µs 3µs 49µs 60µs
Overdrive 1µs 1µs 8µs 10µs
Flexible 8µs to 15µs 3µs to 10µs 49µs 60µs to 74µs
Figure 6c. WRITE-0 TIME SLOT
Speed t
LOW0
t
REC0
t
SLOT
*
Regular 57µs 3µs 60µs
Overdrive 7µs 3µs 10µs
Flexible 57µs 3µs to 10µs 60µs to 67µs
*In a 5V environment (±1V, full temperature range) the tolerance of the internal time base of 1-Wire
slave devices is much narrower than what it is when operated at the minimum voltage of 2.8V. Therefore,
the timing generated by the DS2480B is in compliance with the requirements of all MicroLAN-
compatible 1-Wire devices.
DS2480B
18 of 31
PULSE WAVEFORMS, DISARMED
The Pulse command can be used to generate a strong pullup to 5V and a 12V programming pulse,
respectively. The duration of the pulse is predefined if the parameter value code of parameter 010
(Programming Pulse Duration) has a value from 000 to 110, and parameter 011 (Strong Pullup Duration)
has a value from 000 to 101 (see Table 4). Figures 7a and 7b show the timing of a pulse with predefined
duration, which should be considered the normal case. With dynamic duration the pulse ends as soon as
the current demand of the slave devices on the bus falls below the threshold of the load sensor. If infinite
duration is chosen (parameter value code 111), the host must terminate the Pulse command, as shown in
Figures 7c and 7d. All versions of Figure 7 assume that bit 1 of the pulse command is 0, i.e., disarmed
mode. See the Communication Commands: Pulse section for more details on possibilities of the Pulse
command.
Figure 7a. STRONG PULLUP TO 5V, PREDEFINED DURATION
The processing of a pulse command is essentially the same, regardless if a strong pullup or a
programming pulse is requested. At t
1
the host starts sending the pulse command byte. At t
2
the DS2480B
has received the command and immediately generates the pulse. The pulse ends at t
3
and the DS2480B
sends out the command response byte to inform the host that the command is completed. The idle time
between t
1
and t
2
is determined by the time to transmit the command byte at the selected baud rate. The
idle time between t
3
and t
4
is comprised of the time to transmit the response byte, plus the response time
of the host plus the time to transmit the command and/or data to generate the next time slot.
Figure 7b. 12V PROGRAMMING PULSE, PREDEFINED DURATION
A correct programming pulse can only be generated if the 12V programming voltage is available at the
V
PP
pin of the DS2480B. The rising and falling edges of the programming pulse are actively controlled by
DS2480B. The slew rate is approximately 14V/µs and meets the requirements of 1-Wire EPROM
devices.

DS2480B

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Buffers & Line Drivers
Lifecycle:
New from this manufacturer.
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