PS12017-A Datasheet PS12017-A | P4-P6

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS12017-A

FLAT-BASE TYPE

INSULATED TYPE

Jan. 2000

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V, VDB = 15V, VDL = 5V unless otherwise noted)

(Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only.

(b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit.

(Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The

circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme.

(Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momen-

tarily. The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is

not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to

excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropri-

ately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut

down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back

from its F

O1 pin of the ASIPM indicating a short circuit situation.

SC

OT

OTr

UV

DB

UVDBr

UVDH

UVDHr

OVDH

OVDHr

tdv

IFO(H)

IFO(L)

±IOL

VDL = 5V, VDH = 15V, TC = –20 ~ 100°C

(Note 4)

t

d(read)

ICL(H)

ICL(L)

VDH = 15V

V

DL = 5V

T

C = –20 ~ 100°C (Fig.4)

t

int

VCO

VC+(200%)

VC–(200%)

|∆VCO|

V

C+

VC–

Ratings

—

1

Min.

Trip level

Reset level

Trip level

Reset level

Trip level

Reset level

Trip level

Reset level

Filter time

Over tenperature

protection

Signal output cur-

rent of CL operation

Ic = 0A

Ic = I

OP(200%)

Ic = –IOP(200%)

Allowable input signal dead time

for blocking arm shoot-through

TC ≤ 100°C, Tj ≤ 125°C

V

DH = 15V, VDL = 5V, TC = –20°C ~ +100°C Note 3)

Relates to corresponding inputs (Except brake part)

T

C = –20°C ~ +100°C

Relates to corresponding inputs (Except brake part)

Condition

Symbol Item

Typ. Max.

Unit

Input inter-lock sensing

Offset change area vs temperature

Idle

Active

Supply circuit

under and

over voltage

protection

Idle

Active

Fault output current

kHz

µs

tdead

Analogue signal linearity with

output current

V

DH = 15V, VDL = 5V, TC = –20 ~ 100°C

Analogue signal output voltage limit

Ic > IOP(200%), VDH = 15V,

V

DL = 5V (Fig. 4)

∆V

C

(200%)

Analogue signal overall linear

variation

Analogue signal data hold

accuracy

|V

CO-VC±(200%)|

r

CH

Correspond to max. 500µs data hold period only,

Ic = I

OP(200%) (Fig. 5)

After input signal trigger point (Fig. 8)

Open collector onput

Tj = 25°C (Fig. 7), (Note 5)

V

DL = 5V, VDH = 15V

T

C = –20°C ~ +100°C

Tj ≤ 125°C

Open collector output

4.0

—

1.87

0.77

2.97

—

4.0

—

–5

—

20.4

33.6

100

—

10.0

10.5

11.05

11.55

18.00

16.50

—

65

2.27

1.17

3.37

15

—

1.1

—

3

—

1

25.5

43.0

110

90

11.0

11.5

12.00

12.50

19.20

17.50

10

—

1

15

500

—

100

2.57

1.47

3.67

—

0.7

—

5

—

1

—

30.5

—

120

—

12.0

12.5

12.75

13.25

20.15

18.65

—

1

—

µs

ns

V

mV

V

%

µs

µA

mA

A

°C

V

µs

µA

mA

Analogue signal reading time

CL warning operation level

Short circuit current trip level

f

PWM

txx

PWM input frequency

Allowable input on-pulse width

V5.04.8VDL

VDH, VDB

800

Control supply voltage

—Applied between P-N

Applied between V

DH-GND, CBU+-CBU–, CBV+-CBV–,

C

BW+-CBW–

ConditionSymbol

Item

Ratings

VCC Supply voltage

Min.

RECOMMENDED CONDITIONS

Typ. Max.

Unit

Control supply voltage

Applied between V

DL-GND

13.5

600

15.0

16.5

5.2

V

∆V

DH

, ∆V

DB

,

∆V

DL

VCIN(on)

VCIN(off)

fPWM

tdead

Using application circuit

–1

—

4.8

2

4.0

—

10

—

+1

0.3

—

15

—

V/µs

V

kHz

µs

Supply voltage ripple

Input ON voltage

Input OFF voltage

PWM Input frequency

Arm shoot-through blocking time

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS12017-A

FLAT-BASE TYPE

INSULATED TYPE

Jan. 2000

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

200–200

Analogue output signal

data hold range

1

2

3

4

5

4003001000–100–300–400

0

V

C

+(200%)

V

C0

V

C

–

(200%)

V

C

(V)

V

C

+

V

C

–

min

max

Real load current peak value.(%)(I

c

=I

o

✕ 2)

V

DH

=15V

V

DL

=5V

T

C

=

–

20

~

100˚C

Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-

neously in “LOW” level.

By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F

O” signal is outputted. After an “input

interlock” operation the circuit is latched. The “F

O

” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,

whichever comes in later.

0V

Input signal V

CIN(p)

of each phase upper arm

Input signal V

CIN(n)

of each phase lower arm

Gate signal V

o(p)

of each phase upper arm

(ASIPM internal)

Gate signal V

o(n)

of each phase upper arm

(ASIPM internal)

Error output F

O1

Note : Short circuit protection operation. The protection operates with “FO” flag and reset on a pulse-by-pulse scheme. The protection by

gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).

S

C

delay time

Short circuit sensing signal V

S

Error output F

O1

Gate signal Vo of each phase

upper arm(ASIPM internal)

Input signal V

CIN

of each phase

upper arm

0V

Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING

LINEARITY

Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING

“DATA HOLD” DEFINITION

Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION

Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART

V

CH

(5

µ

s) V

CH

(505

µ

s)

0V

V

C

500µs

r

CH

=

V

CH

(505

µ

s)-V

CH

(5

µ

s)

V

CH

(5

µ

s)

Note ; Ringing happens around the point where the signal output

voltage changes state from “analogue” to “data hold” due

to test circuit arrangement and instrumentational trouble.

Therefore, the rate of change is measured at a 5 µs delayed point.

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS12017-A

FLAT-BASE TYPE

INSULATED TYPE

Jan. 2000

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

U

P

,V

P

,W

P

,U

N

,V

N

,W

N

,Br

F

O1

,F

O2

,F

O3

,CL

CU,CV,CW

GND(Logic)

V

DL

(5V)

ASIPM

CPU

10kΩ

5.1kΩ

0.1nF

R

0.1nF

on

0

V

PN

DC-Bus voltage

Control voltage supply

Boot-strap voltage

N-Side input signal

P-Side input signal

Brake input signal

F

O

1 output signal

V

DB

V

CIN(N)

V

CIN(P)

V

CIN(Br)

F

OI

V

DH, DL

b)

a)

PWM starts

N-side IGBT Current N-side FWDi Current

t(hold)

td(read)

Delay time

+I

CL

–I

CL

on

off

on

off

0

on

off

0

Ref

V

CIN

V(hold)

I

C

(V

S

)

V

C

V

CL

Fig. 9 START-UP SEQUENCE

Normally at start-up, Fo and CL output signals will be pulled-up

High to V

DL voltage (OFF level); however, FO1 output may fall to

Low (ON) level at the instant of the first ON input pulse to an N-Side

IGBT. This can happen particularly when the boot-strap capacitor is

of large size. F

O1 resetting sequence (together with the boot-strap

charging sequence) is explained in the following graph

Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT

a) Boot-strap charging scheme :

Apply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 20µs number of pulses =10 ~ 500 de-

pending on the boot-strap capacitor size)

b) F

O1 resetting sequence:

Apply ON signals to the following input pins : Br → Un/Vn/Wn → Up/Vp/Wp in that order.

Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART.

PS12017-A

PS12017-A

Products related to this Datasheet