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MPC9850VM

P1-P3P4-P6P7-P9P10-P11
Advanced Clock Drivers Devices
6 Freescale Semiconductor
MPC9850
Table 8. LVDS DC Characteristics (T
A
= –40°C to 85°C)
Symbol Characteristics Min Typ Max Unit Condition
Differential LVDS Clock Outputs (QC0, QC0
and QC1, QC1) for V
DD
= 3.3 V ± 5%
V
PP
Output Differential Voltage
(1)
(peak-to-peak) (LVDS)
1. V
PP
is the minimum differential input voltage swing required to maintain AC characteristics including t
PD
and device-to-device skew.
100 400 mV
V
OS
Output Offset Voltage (LVDS) 1050 1600 mV
Table 9. LVPECL DC Characteristics (T
A
= –40°C to 85°C)
(1)
1. AC characteristics are design targets and pending characterization.
Symbol Characteristics Min Typ Max Unit Condition
Differential LVPECL Clock Inputs (CLK1, CLK1
) for V
DD
= 3.3 V ± 0.5%
V
PP
Differential Voltage
(2)
(peak-to-peak) (LVPECL)
2. V
PP
is the minimum differential input voltage swing required to maintain AC characteristics including t
PD
and device-to-device skew.
250 mV
V
CMR
Differential Input Crosspoint Voltage
(3)
(LVPECL)
3. V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
(AC)
range and the input swing lies within the V
PP
(AC) specification. Violation of V
CMR
(AC) or V
PP
(AC) impacts the device propagation delay,
device and part-to-part skew.
1.0 V
DD
– 0.6 V
Table 10. LVCMOS I/O DC Characteristics (T
A
= –40°C to 85°C)
Symbol Characteristics Min Typ Max Unit Condition
LVCMOS for V
DD
= 3.3 V ± 5%
V
IH
Input High Voltage 2.0 V
DD
+ 0.3 V LVCMOS
V
IL
Input Low Voltage 0.8 V LVCMOS
I
IN
Input Current
(1)
1. Inputs have pull-down resistors affecting the input current.
± 200 µAV
IN
= V
DDL
or GND
LVCMOS for V
DD
= 3.3 V ±5%, V
DDOA
= 3.3 V ± 5 and V
DDOB
= 3.3 V ± 5%
V
OH
Output High Voltage 2.4 V I
OH
= –24 mA
V
OL
Output Low Voltage 0.5 V I
OL
= 24 mA
Z
OUT
Output Impedance 14 – 17 Ω
LVCMOS for V
DD
= 3.3 V ±5%, V
DDOA
= 2.5 V ± 5% and V
DDOB
= 2.5 V ± 5%
V
OH
Output High Voltage 1.9 V I
OH
= –15 mA
V
OL
Output Low Voltage 0.4 V I
OL
= 15 mA
Z
OUT
Output Impedance 18 – 22 Ω
MPC9850
Clock Generator for PowerQUICC III NETCOM
IDT™ Clock Generator for PowerQUICC III
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9850
6
Advanced Clock Drivers Devices
Freescale Semiconductor 7
MPC9850
Figure 4. MPC9850 AC Test Reference (LVDS Outputs)
Figure 5. MPC9850 AC Test Reference (LVCMOS Outputs)
Table 11. AC Characteristics (V
DD
= 3.3 V ± 5%, V
DDOA
= 3.3 V ± 5%,V
DDOB
= 3.3 V ± 5%, T
A
= –40°C to +85°C)
(1)
(2)
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50Ω to V
TT
.
Symbol Characteristics Min Typ Max Unit Condition
Input and Output Timing Specification
f
ref
Input Reference Frequency (25 MHz input)
Input Reference Frequency (33 MHz input)
XTAL Input
Input Reference Frequency in PLL Bypass Mode
(3)
3. In bypass mode, the MPC9850 divides the input reference clock.
25
33
25
250
MHz
MHz
MHz
MHz PLL bypass
f
VCO
VCO Frequency Range
(4)
4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: f
ref
= (f
VCO
÷ M) ⋅ N.
2000 MHz
f
MCX
Output Frequency Bank A output
Bank B output
Bank C output
15.87
15.87
50
200
200
500
MHz
MHz
MHz
PLL locked
f
refPW
Reference Input Pulse Width 2 ns
f
refCcc
Input Frequency Accuracy 100 ppm
t
r
, t
f
Output Rise/Fall Time 150 500 ps 20% to 80%
DC Output Duty Cycle 43
47
50
50
57
53
% Bank A and B
Bank C
PLL Specifications
t
LOCK
Maximum PLL Lock Time 10 ms
t
reset_ref
MR Hold Time on Power Up 10 ns
t
reset_pulse
MR Hold Time 10 ns
Skew and Jitter Specifications
t
sk(O)
Output-to-Output Skew (within a bank) 50 ps
t
sk(O)
Output-to-Output Skew (across banks A and B) 400 ps V
DDOA
= 3.3 V
V
DDOB
= 3.3 V
t
JIT(CC)
Cycle-to-Cycle Jitter 200
150
ps
ps
Bank A and B
Bank C
t
JIT(PER)
Period Jitter 200 ps Bank A and C
t
JIT(∅)
I/O Phase Jitter RMS (1 σ) 50 ps Bank A and C
Pulse
Generator
Z = 50Ω
R
T
= 50Ω
Z
O
= 50Ω
DUT MPC9850
V
TT
R
T
= 100Ω
Z
O
= 50Ω
Pulse
Generator
Z = 50Ω
R
T
= 50Ω
Z
O
= 50Ω
DUT MPC9850
V
TT
Z
O
= 50Ω
R
T
= 50Ω
V
TT
MPC9850
Clock Generator for PowerQUICC III NETCOM
IDT™ Clock Generator for PowerQUICC III
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9850
7
Advanced Clock Drivers Devices
8 Freescale Semiconductor
MPC9850
Table 12. MPC9850 Pin Diagram (Top View)
1 2 345678 9 10
A
V
DDOA
V
DDOA
CLKA[1] CLKA[3] CLKA[5] V
DD
QA1 QA2 V
DDOA
V
DDOA
B
V
DDOA
V
DDOA
CLKA[0] CLKA[2] CLKA[4] QA0 V
DDOA
QA3 V
DDOA
V
DDOA
C
RSVD RSVD V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
REF_OUT
D
V
DDA
V
DDA
V
DD
GNDGNDGNDGND V
DD
QC0 QC0
E
REF_SEL CLK V
DD
GNDGNDGNDGND V
DD
V
DDOC
GND
F
PCLK PCLK
V
DD
GNDGNDGNDGND V
DD
QC1 QC1
G
REF_CLK_SEL REF_33MHz V
DD
GNDGNDGNDGND V
DD
PLL_BYPASS MR
H
XTAL_IN XTAL_OUT V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
RIO_C[1] RIO_C[0]
J
V
DDOB
V
DDOB
CLKB[0] CLKB[2] CLKB[4] QB0 V
DDOB
QB3 V
DDOB
V
DDOB
K
V
DDOB
V
DDOB
CLKB[1] CLKB[3] CLKB[5] V
DD
QB1 QB2 V
DDOB
V
DDOB
Table 13. MPC9850 Pin List
Signal
100 Pin
MAPBGA
Signal
100 Pin
MAPBGA
Signal
100 Pin
MAPBGA
Signal
100 Pin
MAPBGA
Signal
100 Pin
MAPBGA
V
DDOA
A1
RSVD
(1)
1. RSVD pins must be left open.
C1 REF_SEL E1 REF_CLK_SEL G1 V
DDOB
J1
V
DDOA
A2
RSVD
(1)
C2 CLK E2 REF_33MHz G2 V
DDOB
J2
CLKA[1] A3 V
DD
C3 V
DD
E3 V
DD
G3 CLKB[0] J3
CLKA[3] A4 V
DD
C4 GND E4 GND G4 CLKB[2] J4
CLKA[5] A5 V
DD
C5 GND E5 GND G5 CLKB[4] J5
V
DD
A6 V
DD
C6 GND E6 GND G6 QB0 J6
QA1 A7 V
DD
C7 GND E7 GND G7 V
DDOB
J7
QA2 A8 V
DD
C8 V
DD
E8 V
DD
G8 QB3 J8
V
DDOA
A9 V
DD
C9 V
DDOC
E9 PLL_BYPASS G9 V
DDOB
J9
V
DDOA
A10 REF_OUT C10 GND E10 MR G10 V
DDOB
J10
V
DDOA
B1 V
DDA
D1 PCLK F1 XTAL_IN H1 V
DDOB
K1
V
DDOA
B2 V
DDA
D2 PCLK F2 XTAL_OUT H2 V
DDOB
K2
CLKA[0] B3 V
DD
D3 V
DD
F3 V
DD
H3 CLKB[1] K3
CLKA[2] B4 GND D4 GND F4 V
DD
H4 CLKB[3] K4
CLKA[4] B5 GND D5 GND F5 V
DD
H5 CLKB[5] K5
QA0 B6 GND D6 GND F6 V
DD
H6 V
DD
K6
V
DDOA
B7 GND D7 GND F7 V
DD
H7 QB1 K7
QA3 B8 V
DD
D8 V
DD
F8 V
DD
H8 QB2 K8
V
DDOA
B9 QC0 D9 QC1 F9 RIO_C[1] H9 V
DDOB
K9
V
DDOA
B10 QC0 D10 QC1 F10 RIO_C[0] H10 V
DDOB
K10
MPC9850
Clock Generator for PowerQUICC III NETCOM
IDT™ Clock Generator for PowerQUICC III
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9850
8
P1-P3P4-P6P7-P9P10-P11

MPC9850VM

Mfr. #:
Buy MPC9850VM
Manufacturer:
IDT
Description:
Clock Generators & Support Products 8 LVCMOS OUT CLOCK GEN
Lifecycle:
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