10©2015 Integrated Device Technology, Inc December 3, 2015
851010 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 851010.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 851010 is the sum of the core power plus the power dissipated in the load(s). The following is the power
dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 105mA = 363.825mW
Power (outputs)
MAX
= 44.5mW/Loaded Output Pair
If all outputs are loaded, the total power is 10 * 44.5mW = 445mW
Total Power_
MAX
(3.465V, with all outputs switching) = 363.825mW + 445mW = 808.825mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 65.7°C/W per Table 4 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.809W * 65.7°C/W = 123.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 4. Thermal Resistance
JA
for 32 Lead LQFP, Forced Convection
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 65.7°C/W 55.9°C/W 52.4°C/W
11©2015 Integrated Device Technology, Inc December 3, 2015
851010 Datasheet
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 5.
VDD
V
OUT
R
L
50Ω
IC
I
OUT
= 17mA
R
REF
=
950
Ω ± 1%
Figure 5. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,
use the following equations which assume a 50 load to ground.
The highest power dissipation occurs when V
DD
_
MAX
.
Power = (V
DD_MAX
– V
OUT
) * I
OUT
,
since V
OUT
– I
OUT
* R
L
= (V
DD_MAX
– I
OUT
* R
L
) * I
OUT
= (3.465V – 17mA * 50) * 17mA
Total Power Dissipation per output pair = 44
.5mW
12©2015 Integrated Device Technology, Inc December 3, 2015
851010 Datasheet
Reliability Information
Table 5.
JA
vs. Air Flow Table for a 32 Lead LQFP
Transistor Count
The transistor count for 851010 is: 843
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 65.7°C/W 55.9°C/W 52.4°C/W

851010AYLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 10 HCSL OUT BUFFER
Lifecycle:
New from this manufacturer.
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