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NB7V32MMNTXG

P1-P3P4-P6P7-P9
© Semiconductor Components Industries, LLC, 2010
August, 2010 − Rev. 5
1 Publication Order Number:
NB7V32M/D
NB7V32M
1.8V / 2.5V, 10GHz ÷2 Clock
Divider with CML Outputs
Multi−Level Inputs w/ Internal
Termination
Description
The NB7V32M is a differential B2 Clock divider with
asynchronous reset. The differential Clock inputs incorporate internal
50 W termination resistors and will accept LVPECL, CML and LVDS
logic levels.
The NB7V32M produces a B2 output copy of an input Clock
operating up to 10 GHz with minimal jitter.
The RESET Pin is asserted on the rising edge. Upon power−up, the
internal flip−flops will attain a random state; the Reset allows for the
synchronization of multiple NB7V32M’s in a system.
The 16 mA differential CML output provides matching internal
50 W termination which guarantees 400 mV output swing when
externally receiver terminated with 50 W to V
CC
.
The NB7V32M is the 1.8 V/2.5 V version of the NB7L32M
(2.5 V/3.3 V) and is offered in a low profile 3 mm x 3 mm 16−pin
QFN package. The NB7V32M is a member of the GigaComm™
family of high performance clock products. Application notes,
models, and support documentation are available at
www.onsemi.com
.
Features
• Maximum Input Clock Frequency > 10 GHz, typical
• Random Clock Jitter < 0.8 ps RMS
• 200 ps Typical Propagation Delay
• 35 ps Typical Rise and Fall Times
• Differential CML Outputs, 400 mV Peak−to−Peak, Typical
• Operating Range: V
CC
= 1.71 V to 2.625 V with GND = 0 V
• Internal 50 W Input Termination Resistors
• QFN−16 Package, 3 mm x 3 mm
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN−16
MN SUFFIX
CASE 485G
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
1
NB7V
32M
ALYWG
G
16
1
Figure 1. Simplified Logic Diagram
Q
Q
RESET
B2
50W
50W
CLK
VTCLK
CLK
VTCLK
VREFAC
R
NB7V32M
http://onsemi.com
2
VREFAC GND GND GND
VCC R VCC VCC
VCC
Q
Q
VCC
VTCLK
CLK
CLK
5678
16 15 14 13
12
11
10
9
1
2
3
4
NB7V32M
Exposed Pad (EP)
Figure 2. Pin Configuration (Top View)
VTCLK
Table 1. TRUTH TABLE
CLK CLK R Q Q
x x H L H
Z W L CLK B 2 CLK B 2
Z = LOW to HIGH Transition
W = HIGH to LOW Transition
x = Don’t Care
Table 2. PIN DESCRIPTION
Pin Name I/O Description
1 VTCLK −
Internal 50 W Termination Pin for CLK
2 CLK LVPECL, CML,
LVDS Input
Non−inverted Differential CLK Input. (Note 1)
3 CLK LVPECL, CML,
LVDS Input
Inverted Differential CLK Input. (Note 1)
4 VTCLK −
Internal 50 W Termination Pin for CLK
5 VREFAC − Internally Generated Output Voltage Reference for Capacitor−Coupled Inputs, only
6 GND − Negative Supply Voltage
7 GND − Negative Supply Voltage
8 GND − Negative Supply Voltage
9 VCC − Positive Supply Voltage. (Note 2)
10 Q CML Output Inverted Differential Output
11 Q CML Output Non−Inverted Differential Output
12 VCC − Positive Supply Voltage. (Note 2)
13 VCC − Positive Supply Voltage. (Note 2)
14 VCC − Positive Supply Voltage. (Note 2)
15 R LVCMOS Input
Asynchronous Reset Input. Internal 75 kW pulldown to GND.
16 VCC − Positive Supply Voltage. (Note 2)
− EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for im-
proved heat transfer out of package. The exposed pad must be attached to a heat−sinking con-
duit. The pad is electrically connected to the die, and must be electrically and thermally connected
to GND on the PC board.
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage or left open,
and if no signal is applied on CLK/CLK
input, then the device will be susceptible to self−oscillation. Q/Q outputs have internal 50 W source
termination resistors.
2. VCC and GND pins must be externally connected to a power supply for proper operation.
NB7V32M
http://onsemi.com
3
Table 3. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
> 4 kV
> 200 V
Moisture Sensitivity 16−QFN Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 164
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Positive Power Supply GND = 0 V 3.0 V
V
IN
Positive Input Voltage GND = 0 V −0.5 to V
CC
+ 0.5 V V
V
INPP
Differential Input Voltage |D − D| 1.89 V
I
IN
Input Current Through R
T
(50 W Resistor)
$40 mA
I
OUT
Output Current Through R
T
(50 W Resistor)
$40 mA
I
VREFAC
VREFAC Sink/Source Current $1.5 mA
T
A
Operating Temperature Range −40 to +85
°C
T
stg
Storage Temperature Range −65 to +150
°C
q
JA
Thermal Resistance (Junction−to−Ambient)
(Note 3)
0 lfpm
500 lfpm
QFN−16
QFN−16
42
35
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case)
(Note 3)
QFN−16 4
°C/W
T
sol
Wave Solder Pb−Free 265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
P1-P3P4-P6P7-P9

NB7V32MMNTXG

Mfr. #:
Buy NB7V32MMNTXG
Manufacturer:
ON Semiconductor
Description:
Clock Drivers & Distribution 1.8/2.5V DIV BY 2
Lifecycle:
New from this manufacturer.
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