ISL6700IB

4
FN9077.6
December 29, 2004
Absolute Maximum Ratings Thermal Information
Supply Voltage, V
DD
(Note 1) . . . . . . . . . . . . . . . . . . . -0.3V to 16V
LI and HI Voltages (Note 1) . . . . . . . . . . . . . . . . -0.3V to V
DD
+0.3V
Voltage on HS (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 80V
Voltage on HB (Note 1) . . . . . . . . . . . . . . . . V
HS
-0.3V to V
HS
+V
DD
Voltage on LO (Note 1) . . . . . . . . . . . . . . . . . V
SS
-0.3 to V
DD
+0.3V
Voltage on HO (Note 1) . . . . . . . . . . . . . . . . V
HS
-0.3V to V
HB
+0.3V
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
Maximum Recommended Operating Conditions
Supply Voltage, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 15V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 75V
Voltage on HS (Note 2) . . . . . . . . . .(Repetitive Transient) -1V to 80V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . V
HS
+7.5V to V
HS
+V
DD
Thermal Resistance (Typical) θ
JA
(°C/W) θ
JC
(°C/W)
SOIC (Note 3) . . . . . . . . . . . . . . . . . . . 95 N/A
QFN (Note 4) . . . . . . . . . . . . . . . . . . . . 49 7
Max Power Dissipation at 25°C in Free Air (SOIC, Note 3). 1.316W
Max Power Dissipation at 25°C in Free Air (QFN, Note 4) . .2.976W
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature Range . . . . . . . . . -40°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.
NOTES:
1. All voltages referenced to V
SS
unless otherwise specified.
2. Based on V
DD
=15V. The magnitude of the allowable negative transient on the HS pin is a function of the V
DD
supply voltage. V
HS
<15.6V-
V
DD
+V
F
, where V
HS
is the magnitude of the allowable negative transient and V
F
is the forward voltage drop of the bootstrap diode.
3. θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θ
JC
,
the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, No Load on LO or HO, Unless Otherwise Specified
PARAMETERS SYMBOL TEST CONDITIONS
T
J
= 25°C
T
J
= -40°C TO
125°C
UNITSMIN TYP MAX MIN MAX
SUPPLY CURRENTS & UNDERVOLTAGE PROTECTION
V
DD
Quiescent Current I
DD
LI = 0 or V
DD
- 1.9 2.2 - 2.4 mA
V
DD
Operating Current I
DDO
f = 50kHz - 2.0 2.2 - 2.5 mA
V
DD
Operating Current I
DDO
f = 500kHz - 2.5 3.0 - 4.0 mA
HB Off Quiescent Current I
HBL
HI = 0 - 1.25 1.5 - 1.8 mA
HB On Quiescent Current I
HBH
HI = V
DD
- 170 240 - 250 µA
HB Operating Current I
HBO
f = 50kHz, C
L
= 1000pF - 1.45 1.8 - 2.0 mA
HB Operating Current I
HBO
f = 500kHz, C
L
= 1000pF - 2.4 2.8 - 3.0 mA
HS Leakage Current I
HLK
V
HS
= 80V
V
HB
= 96V
--1-1µA
V
DD
Rising Undervoltage Threshold V
DDUV+
6.8 7.6 8.25 6.5 8.5 V
V
DD
Falling Undervoltage Threshold V
DDUV-
6.5 7.1 7.8 6.25 8.1 V
Undervoltage Hysteresis UVHYS 0.17 0.45 0.75 0.15 0.90 V
HB Undervoltage Threshold VHBUV Referenced to HS 4.8 5.3 6.5 4.0 7.5 V
INPUT PINS: LI and HI
Low Level Input Voltage V
IL
Full Operating Conditions 0.8 1.6 - 0.8 - V
High Level Input Voltage V
IH
Full Operating Conditions - 1.7 2.2 - 2.2 V
Input Voltage Hysteresis - 100 - - - mV
Low Level Input Current I
IL
V
IN
= 0V, Full Operating Conditions -70 -60 -30 -80 -30 µA
High Level Input Current I
IH
V
IN
= 5V, Full Operating Conditions 30 115 130 30 145 µA
ISL6700
5
FN9077.6
December 29, 2004
GATE DRIVER OUTPUT PINS: LO & HO
Low Level Output Voltage V
OL
I
OUT
= 0A - - 0.1 - 0.1 V
High Level Output Voltage V
DD
-V
OH
I
OUT
= 0A - - 0.1 - 0.1 V
Peak Pullup Current I
O
+V
OUT
= 0V - 1.4 - - - A
Peak Pulldown Current I
O
-V
OUT
= 12V - 1.3 - - - A
Electrical Specifications V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, No Load on LO or HO, Unless Otherwise Specified (Continued)
PARAMETERS SYMBOL TEST CONDITIONS
T
J
= 25°C
T
J
= -40°C TO
125°C
UNITSMIN TYP MAX MIN MAX
Switching Specifications V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, No Load on LO or HO, Unless Otherwise Specified
PARAMETERS SYMBOL
TEST
CONDITIONS
T
J
= 25°C
T
J
= -40°C
TO 125°C
UNITSMIN TYP MAX MIN MAX
Lower Turn-off Propagation Delay
(LI Falling to LO Falling)
t
LPHL
- 45 50 - 65 ns
Upper Turn-off Propagation Delay
(HI Falling to HO Falling)
t
HPHL
- 60 75 - 90 ns
Lower Turn-on Propagation Delay
(LI Rising to LO Rising)
t
LPLH
- 75 82 - 95 ns
Upper Turn-on Propagation Delay
(HI Rising to HO Rising)
t
HPLH
- 70 75 - 95 ns
Deadtime, (t
HPLH
- t
LPHL
)DHt
ON
LI, HI switched simultaneously 0 24 - 0 - ns
Deadtime, (t
LPLH
- t
HPHL
)DLt
ON
017- 0 - ns
Rise Time t
R
-520-25ns
Fall Time t
F
-520-25ns
Delay Matching: Lower Turn-On and Upper Turn-Off t
MON
-820-25ns
Delay Matching: Lower Turn-Off and Upper Turn-On t
MOFF
- -15 25 - 30 ns
Pin Descriptions
SYMBOL DESCRIPTION
V
DD
Positive supply to control logic and lower gate drivers. De-couple this pin to V
SS
. Connect anode of bootstrap diode to this pin.
HI Logic level input that controls the HO output.
LI Logic level input that controls the LO output.
V
SS
Chip negative supply, generally will be ground.
LO Low-side output. Connect to gate of low-side power MOSFET.
HS High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this
pin.
HO High-side output. Connect to gate of high-side power MOSFET.
HB High-side bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive
side of bootstrap capacitor to this pin.
EPAD Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
ISL6700
6
FN9077.6
December 29, 2004
Timing Diagrams
FIGURE 3.
FIGURE 4.
t
HPLH
,
t
LPLH
t
HPHL
,
t
LPHL
HI,
LI
HO,
LO
t
MON
t
MOFF
LI
HI
LO
HO
ISL6700

ISL6700IB

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC DRIVER HALF BRIDGE DUAL 8SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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