AD7861
REV. B
–5–
ANALOG INPUT BLOCK
The AD7861 is an 11-bit resolution, successive approximation
analog-to-digital (A/D) converter with twos complement output
data format. The analog input range is 0 V–5 V with a 2.5 V
reference as defined by the reference input pin (REFIN). The
AD7861 has an internal 2.5 V ± 5% reference, which is utilized
by connecting the reference output pin (REFOUT) to the
REFIN pin.
The A/D conversion time is determined by the system clock
frequency, which can range from 6.25 MHz to 12.5 MHz.
Forty clock cycles are required to complete each conversion.
There is a 4-channel simultaneous sample and hold amplifier
(SHA) at the AD7861 input stage. This allows up to 4 channels to
be simultaneously held and sequentially digitized. The SHA
acquisition time is 20 clock cycles and is independent of the
number of channels sampled.
The minimum throughput time can be calculated as follows:
t
AA
= t
SHA
+ (n × t
CONV
)
where t
AA
= analog acquisition time, t
SHA
= SHA acquisition
time, n = # channels, t
CONV
= conversion time per channel
(40 clock cycles).
A/D conversions are initiated by an external analog sample
clock pin (CONVST).
The CONVST input can be run asynchronous to the AD7861
system clock. When CONVST is run asynchronous from CLK,
the falling edge of CLK subsequent to CONVST high initiates
the conversion.
BUSY
The AD7861 BUSY pin goes low at the start of conversion, and
remains low for 40 clock cycles per channel. When BUSY goes
high, this indicates that the output data buffers have been
updated. Data from the previous conversion can be read up to
(n × 40 – 1) clock cycles after the start of conversion (n =
number of channels converted). Refer to Figure 3.
t
= 1 CLOCK CYCLE
t
= (n x 40 –1) CLOCK CYCLES
t
= n x 40 CLOCK CYCLES
(n x 40 –1) CLOCK CYCLES
OLD DATA VALID NEW DATA VALID
CLK
BUSY
CONVST
DATA
Figure 3. Busy Pulse Timing
CHANNEL SELECTION
Determining which channels are converted is dependent on the
settings of M0 and M1. The available channel combinations are:
M1 M0 Channels Converted
0 0 VIN2, VIN3
0 1 VIN2, VIN3, AUX
1 0 VIN1, VIN2, VIN3
1 1 VIN1, VIN2, VIN3, AUX
The user must select which channels to convert using M0/M1, a
minimum of two clock cycles before the start of conversion.
The AD7861 provides 4 auxiliary input channels which can be
individually multiplexed into the auxiliary ADC channel. Pins S0/
S1 are used to multiplex these auxiliary channels according to the
following table. It is important to note that the ADC performs a
series of conversions based on the input voltage on each pin
(including the AUX pin) at the start of the CONVST conversion
pulse. The user must select the auxiliary channel using S0/S1
a minimum of two clock cycles before the start of the conversion
sequence.
S1 S0 Channel Selected
0 0 AUX0
0 1 AUX1
1 0 AUX2
1 1 AUX3
DIGITAL INTERFACE
The AD7861 is designed to interface with the ADSP-21xx
family of DSPs. The 12-bit parallel interface can also be used
with other DSPs and microcontrollers.
The 11-bit A/D conversion output occupies the 11 most
significant bits of the 12-bit interface. The LSB (Data Bit 0) is
tied low.
REGISTER BASED INPUT/OUTPUT
To facilitate integration into most designs, a register based
input/output structure is provided. These registers can be
memory mapped into the user’s system along with other
memory mapped peripherals.
REGISTER ADDRESSING
Two address lines (A0 through A1) are used in conjunction with
control lines (CS, RD) to select registers VIN1, VIN2, VIN3, or
AUX. These control lines are active low. Timing and logical
sense is as for the ADSP-2100 family.
Pin Function
CS Enables the AD7861 Register Interface
RD Places the Internal Register on the Data Bus
REGISTER LISTING
The output of each channel is stored in its respective register.
The symbolic names and address locations are listed in the
following table.
Name A1 A0 Register Function
VIN1 0 0 A/D Conversion Result Channel VIN1
VIN2 0 1 A/D Conversion Result Channel VIN2
VIN3 1 0 A/D Conversion Result Channel VIN3
AUX 1 1 A/D Conversion Result Channel AUX
