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ADCMP395ARMZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
Data Sheet ADCMP394/ADCMP395/ADCMP396
Rev. B | Page 13 of 18
WINDOW COMPARATOR FOR NEGATIVE
VOLTAGE MONITORING
Figure 35 shows the circuit configuration for negative supply
voltage monitoring. To monitor a negative voltage, a reference
voltage is required to connect to the end node of the voltage
divider circuit, in this case, REF.
Figure 35. Negative Undervoltage/Overvoltage Monitoring Configuration
Equation 7, Equation 9, and Equation 10 need some minor
modifications. The reference voltage, V
REF
, is added to the
overall voltage drop; therefore, it must be subtracted from V
M
,
V
UV
, and V
OV
before using each of them in Equation 7, Equation 9,
and Equation 10.
To monitor a negative voltage level, the resistor divider circuit
divides the voltage differential level between V
REF
and the
negative supply voltage into the high-side voltage, V
NH
, and the
low-side voltage, V
NL
. The high-side voltage, V
NH
, is connected
to INA+, and the low-side voltage, V
NL
, is connected to INB−.
To trigger an overvoltage condition, the monitored voltage must
exceed the nominal voltage in terms of magnitude, and the
high-side voltage (in this case, V
NH
) on the INA+ pin must be
more negative than ground. Calculate the high-side voltage,
V
NH
, by using the following formula:

OV
Z
YX
YX
OV
REFNH
V
RRR
RR
VVGNDV
(11)
In addition,
M
REFM
Z
YX
I
VV
RRR
(12)
Therefore, R
Z
, which sets the desired trip point for the
overvoltage monitor, is calculated by

OV
REFM
REFMREF
Z
VVI
VVV
R
(13)
To trigger an undervoltage condition, the monitored voltage
must be less than the nominal voltage in terms of magnitude,
and the low-side voltage (in this case, V
NL
) on the INB− pin
must be more positive than ground. Calculate the low-side
voltage, V
NL
, by the following:

UV
Z
YX
X
UVREFNL
V
RRR
R
VVGNDV
(14)
Because R
Z
is already known, R
Y
can be expressed as follows:

Z
UVREFM
REFMREF
Y
R
VVI
VVV
R
(15)
When R
Y
and R
Z
are known, R
X
is then calculated by
Z
Y
M
REFM
X
RR
I
VV
R
(16)
PROGRAMMABLE SEQUENCING CONTROL CIRCUIT
The circuit shown in Figure 36 is used to control power supply
sequencing. The delay is set by the combination of the pull-up
resistor (R
PULLUP
), the load capacitor (C
L
), and the resistor
divider network.
Figure 36. Programmable Sequencing Control Circuit
Figure 37 shows a simple block diagram for a programmable
sequencing control circuit. The application delays the enable signal,
EN, of the external regulators (LDO x) in a linear order when
the open-drain signal (SEQ) changes from low to high impedance.
The ADCMP394/ADCMP395/ADCMP396 have a defined output
state during startup, which prevents any regulator from turning
on if V
CC
is still below the UVLO threshold.
Figure 37. Simplified Block Diagram of a Programmable
Sequencing Control Circuit
OUTA
INA+
REF
INA–
OUTB
INB+
INB–
R
X
R
Y
R
Z
V
NL
V
NH
V
M
12209-235
C
L
OUTA
OUTB
OUTC
OUTD
R2
V2
R3
V3
R4
V4
R5
R1
V1
R
PULL-UP
V
REF
/V
CC
SEQ
U1
INA+
INA–
INB+
INB–
INC+
INC–
IND+
IND–
12209-236
IN
EN
OUT
GND
LDO 1
3.0V3.3V
IN
EN
OUT
GND
LDO 2
1.8V
IN
EN
OUT
GND
LDO 3
2.5V
IN
EN
OUT
GND
LDO 4
1.2V
GND
V
REF
/V
CC
SEQ
t
1
t
2
t
3
t
4
12209-237
ADCMP394/ADCMP395/ADCMP396 Data Sheet
Rev. B | Page 14 of 18
Figure 38. Programmable Sequencing Control Circuit Timing Diagram
When the SEQ signal changes from low to high impedance, the
load capacitor, C
L
, starts to charge. The time it takes to charge the
load capacitor to the pull-up voltage (in this case, V
REF
or V
CC
) is the
maximum delay programmable in the circuit. It is recommended
to have the threshold within 10% to 90% of the pull-up voltage.
Calculate the maximum allowable delay by
t
MAX
= 2.2R
PULLUP
C
LOAD
(17)
The delay of each output is changed by changing the threshold
voltage, V1 to V4, when the comparator changes its output state.
To calculate the voltage thresholds for the comparator, use the
following formulas:
LPULLUP
1
CR
t
REF
eVV1 1
(18)
LPULLUP
CR
t
REF
eVV2
2
1
(19)
LPULLUP
CR
t
REF
eVV3
3
1
(20)
LPULLUP
4
CR
t
REF
eVV4 1
(21)
The threshold voltages can come from a voltage reference or a
voltage divider circuit, as shown in Figure 36.
First, determine the allowable current, I
DIV
, flowing through the
resistor divider. After the value for I
DIV
is determined, calculate
R1, R2, R3, R4, and R5 using the following formulas:
R5R4R3R2R1
I
V
R
DI
V
REF
DIV
(22)
REF
DIV
V
V1R
R1
(23)
R1
V
V2R
R2
RE
F
DIV
(24)
R2R1
V
V3R
R3
RE
F
DIV
(25)
R3R2R1
V
V4R
R
RE
F
DIV
4
(26)
R5 = R
DIV
− R1 − R2 − R3 − R4 (27)
To create a mirrored voltage sequence, add a resistor (R
MIRROR
)
between the pull-up resistor (R
PULLUP
) and the load capacitor
(C
L
) as shown in Figure 39.
Figure 39. Circuit Configuration for a Mirrored Voltage Sequencer
Figure 39 shows the circuit configuration for a mirrored voltage
sequencer. When SEQ changes from low to high impedance, the
response is similar to Figure 38. When SEQ changes from high
to low impedance, the load capacitor (C
L
) starts to discharge at
a rate set by R
MIRROR
. The delay of each comparator is dependent
on the threshold voltage previously set for t
1
to t
4
. The result is a
mirrored power-down sequence.
SEQ
V
C
L
OUT4
OUT3
OUT2
OUT1
V1
V2
V3
V4
t
4
t
3
t
2
t
1
12209-238
C
L
OUT4
OUT3
OUT2
OUT1
R2
V2
R3
V3
R4
V4
R5
R1
V1
R
PULL-UP
V
REF
/V
CC
U1
U2
INA+
INA–
INB+
INB–
INA+
INA–
INB+
INB–
12209-239
S
EQ
R
MIRROR
Data Sheet ADCMP394/ADCMP395/ADCMP396
Rev. B | Page 15 of 18
Figure 40. Mirrored Voltage Sequencer Timing Diagram
The timing diagram for the mirrored voltage sequencer is
shown in Figure 40.
Equation 18 through Equation 21 must account for the additional
resistance, R
MIRROR
, in the calculations of the voltage thresholds.
To calculate these new thresholds, see Equation 28 through
Equation 31.

L
MIRROR
PULLUP
1
CRR
t
REF
eVV1 1 (28)

L
MIRROR
PULLUP
2
CRR
t
REF
eVV2 1
(29)

L
MIRROR
PULLUP
3
CRR
t
REF
eVV3 1
(30)

L
MIRROR
PULLUP
4
CRR
t
REF
eVV4 1
(31)
R
MIRROR
provides the mirrored delay by prolonging the discharge
time of the capacitor. The mirrored voltage sequencer uses the
same threshold in Equation 28 to Equation 31 in a decreasing
order. To calculate the exact value of the mirrored delay time,
see Equation 32 through Equation 35.
REF
L
MIRROR
5
V
V
CRt
4
ln
(32)
REF
L
MIRROR
6
V
V
CRt
3
ln
(33)
REF
L
MIRROR
7
V
V
CRt
2
ln
(34)
REF
L
MIRROR
8
V
V1
CRt ln
(35)
MIRRORED VOLTAGE SEQUENCER EXAMPLE
To illustrate how the mirrored voltage sequencer works, see
Figure 37 and then consider a system that uses a V
REF
of 1 V and
requires a delay of 50 ms when SEQ changes from low to high
impedance, and between each regulator when turning on. These
considerations require a rise time of at least 200 ms for the pull-up
resistor (R
PULLUP
) and the load capacitor (C
L
). The sum of the
resistance of R
MIRROR
and R
PULLUP
must be large enough to charge the
capacitor longer than the minimum required delay. For a
symmetrical mirrored power-down sequence, the value of R
MIRROR
must be much larger than R
PULLUP
. A 10 kΩ R
PULLUP
value limits the
pull-down current to 100 μA while giving a reasonable value for
R
MIRROR
. A typical 1 μF capacitor together with a 150 kΩ R
MIRROR
value gives a value of
t
MAX
= 2.2((160 × 10
3
) × (1 × 10
−6
)) = 351 ms (36)
The threshold voltage required by each comparator is set by
Equation 28 to Equation 31. For example,
6
101
3
10160
3
1050
eVV1
REF
1
where V1 = 268.38 mV.
Therefore, V2 = 464.74 mV, V3 = 608.39 mV, and V4 =
713.5 mV.
Next, consider 10 μA as the maximum current (I
DIV
) flowing
through the resistor divider network. This current gives the total
resistance of the divider network (R
DIV
) and the individual
resistor values using Equation 22 to Equation 27, resulting in
the following:
R
DIV
= 100 kΩ
R1 = 26.84 kΩ ≈ 26.7 kΩ
R2 = 19.64 kΩ ≈ 19.6 kΩ
R3 = 14.37 kΩ ≈ 14.3 kΩ
R4 = 10.51 kΩ ≈ 10.5 kΩ
R5 = 28.65 kΩ ≈ 28.7 kΩ
SEQ
V
C
L
OUT4
OUT3
OUT2
OUT1
t
4
t
3
t
2
t
7
t
8
t
1
t
5
t
6
V1
V2
V3
V4
V4
V3
V2
V1
12209-240
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

ADCMP395ARMZ

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Analog Comparators Dual Comparator a nd reference
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