MC74VHCT02AMG

© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 6
1 Publication Order Number:
MC74VHCT02A/D
MC74VHCT02A
Quad 2-Input NOR Gate
The MC74VHCT02A is an advanced high speed CMOS 2−input
NOR gate fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5 V CMOS level output swings.
The VHCT02A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when V
CC
= 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems
to 3 V systems.
Features
High Speed: t
PD
= 3.6 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 2 μA (Max) at T
A
= 25°C
TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2 V to 5.5 V Operating Range
Low Noise: V
OLP
= 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 40 FETs or 10 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
MARKING
DIAGRAMS
TSSOP−14
DT SUFFIX
CASE 948G
1
SOIC−14
D SUFFIX
CASE 751A
1
http://onsemi.com
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G = Pb−Free Package
VHCT02AG
AWLYWW
1
14
VHCT
02A
ALYWG
G
1
14
(Note: Microdot may be in either location)
Device Package Shipping
ORDERING INFORMATION
MC74VHCT02ADR2G SOIC−14
(Pb−Free)
TSSOP14
(Pb−Free)
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
MC74VHCT02ADTR2G 2500 / Tape &
Reel
2500 / Tape &
Reel
MC74VHCT02A
http://onsemi.com
2
Figure 1. LOGIC DIAGRAM
1
Y1
2
A1
3
B1
Y4
Y = A + B
4
Y2
5
A2
6
B2
10
Y3
8
A3
9
B3
13
11
A4
12
B4
FUNCTION TABLE
A
L
L
H
H
Inputs Output
B
L
H
L
H
Y
H
L
L
L
Figure 2. PIN ASSIGNMENT
11
12
13
14
8
9
105
4
3
2
1
7
6
Y3
A4
B4
Y4
V
CC
A3
B3
Y2
B1
A1
Y1
GND
B2
A2
MC74VHCT02A
http://onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage – 0.5 to + 7.0 V
V
in
DC Input Voltage – 0.5 to + 7.0 V
V
out
DC Output Voltage – 0.5 to V
CC
+ 0.5 V
I
IK
Input Diode Current − 20 mA
I
OK
Output Diode Current ± 20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 50 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature – 65 to + 150
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
Derating SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 4.5 5.5 V
V
in
DC Input Voltage 0 5.5 V
V
out
DC Output Voltage 0 V
CC
V
T
A
Operating Temperature − 40 + 85
_C
t
r
, t
f
Input Rise and Fall Time V
CC
=5.0V ±0.5V 0 20 ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not
implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may
affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Symbo
l
Parameter Test Conditions
V
CC
(V)
T
A
= 25°C T
A
85°C T
A
125°C
Uni
t
Min Typ Max Min Max Min Max
V
IH
Minimum High−Level Input
Voltage
3.0
4.5
5.5
1.2
2.0
2.0
1.2
2.0
2.0
1.2
2.0
2.0
V
V
IL
Maximum Low−Level Input
Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
V
OH
Minimum High−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
= − 50μA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
V
IN
= V
IH
or V
IL
I
OH
= − 4mA
I
OH
= − 8mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
OL
Maximum Low−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OL
= 50μA
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
I
OL
= 4mA
I
OL
= 8mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
IN
Maximum Input Leakage
Current
V
IN
= 5.5 V or
GND
0 to 5.5 ± 0.1 ± 1.0 ± 1.0 μA
I
CC
Maximum Quiescent Supply
Current
V
IN
= V
CC
or GND 5.5 2.0 20 40 μA
I
CCT
Quiescent Supply Current Input: V
IN
= 3.4V 5.5 1.35 1.50 1.65 mA
I
OPD
Output Leakage Current V
OUT
= 5.5V 0.0 0.5 5.0 10 μA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.

MC74VHCT02AMG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Logic Gates 5V Quad 2-Input NOR
Lifecycle:
New from this manufacturer.
Delivery:
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