LTC4218CGN#TRPBF Datasheet LTC4218IGN#PBF, LTC4218IDHC-12#PBF, LTC4218CDHC-12#PBF | P10-P12

LTC4218

4218fh

For more information www.linear.com/LTC4218

applications inForMation

The typical LTC4218 application is in a high availability

system that uses a positive voltage supply to distribute

power to individual cards. The basic application circuit

is shown in Figure 1. External component selection is

discussed in detail in the following sections.

Figure 2. Supply Turn-On

Figure 1. 3A, 12V Card Resident Application

Turn-On Sequence

The power supply on a board is controlled by placing

an external N-channel pass transistor (Q1) in the power

path. Note the sense resistor (R

) detects current and

the capacitor (C

GATE

) controls gate slew rate. Resistor R1

prevents high frequency oscillations in Q1 and resistor

GATE

isolates C

GATE

during fast turn-off.

Several conditions must be present before the external

pass transistor can be turned on. First, the supply V

must exceed its undervoltage lockout level. Next, the

internally generated supply INTV

must cross its 2.65V

undervoltage threshold. This generates a 25µs power-

on-reset pulse which clears the logic’s fault register and

initializes internal latches.

After the power-on-reset pulse, the UV and OV pins must

indicate that the input voltage is within the acceptable

range. All of these conditions must be satisﬁed for a dura

tion of 100ms to ensure that any contact bounce during

the insertion has ended.

The pass transistor is turned on by charging up the GATE

with a 24µA charge pump generated current sour

(Figure 2).

The voltage at the GATE pin rises with a slope equal to

24µA/C

GATE

and the supply inrush current is set at:

INRUSH

GATE

• 24µA

When the GATE voltage reaches the MOSFET threshold

voltage, the switch begins to turn on and the SOURCE

voltage follows the GATE voltage as it increases. Once

SOURCE reaches V

, the GATE will ramp up until clamped

by the 6.15V zener between GATE and SOURCE.

As the SOURCE pin voltage rises, so will the FB pin which

is monitoring it. If the voltage across the current sense

resistor (R

) gets too high, the inrush current will be limited

by the internal current limiting circuitry. Once the FB pin

crosses its 1.235V threshold and the GATE to SOURCE

voltage exceeds 4.2V, the PG pin will cease to pull low and

indicate that the power is good.

Turn-Off Sequence

The switch can be turned off by a variety of conditions. A

normal turn-off is initiated by the UV pin going below its

1.235V threshold. Additionally, several fault conditions will

turn off the switch. These include an input overvoltage (OV

pin) and overcurrent circuit breaker (SENSE pin). Normally,

the switch is turned off with a 250µA current pulling down

the GATE pin to ground. With the switch turned off, the

SOURCE pin voltage drops which pulls the FB pin below

its threshold. The PG then pulls low to indicate output

power is no longer good.

t1 t2

SLOPE = 24µA/C

GATE

SOURCE

+ 6.15V

4218 F02

150k

20k

ADC

226k

1µF

20k

12V

4218 F01

10k

10Ω

0.1µF

330µF

OUT

12V

UV = 9.88V

OV = 15.2V

PG = 10.5V

GND

MON

SET

20k

0.1µF

2mΩ

Si7108DN

MON

20k

SET

GATE

0.01µF

GATE

GATE SOURCESENSE

–

SENSE

LTC4218GN

INTV

TIMER

F LT

140k

20k

*TVS Z1: DIODES INC SMAJ17A

Z1*

LTC4218

4218fh

For more information www.linear.com/LTC4218

applications inForMation

If V

drops below 2.65V for greater than 5µs or INTV

drops below 2.5V for greater than 1µs, a fast shutdown

of the switch is initiated. The GATE is pulled down with a

170mA current to the SOURCE pin.

Overcurrent Fault

The LTC4218 features an adjustable current limit with

foldback that protects the MOSFET when excessive load

current happens. To protect the switch during active cur

rent limit, the available current is reduced as a function

the output

voltage sensed by the FB pin. A graph in the

Typical Performance Characteristics shows the Current

Limit Threshold Foldback.

An overcurrent fault occurs when the current limit circuitry

has been engaged for longer than the time-out delay set by

the TIMER. Current limiting begins when the current sense

voltage between the SENSE

and SENSE

–

pins reaches

3.75mV to 15mV (depending on the foldback). The GATE

pin is then brought down with a 170mA GATE-to-SOURCE

current. The voltage on the GATE is regulated in order to

limit the current sense voltage to less than 15mV. At this

point, a circuit breaker time delay starts by charging the

external timing capacitor with a 100µA pull-up current from

the TIMER pin. If the TIMER pin reaches its 1.2V threshold,

the external switch turns off (with a 250µA current from

GATE to ground). Next, the F LT pin is pulled low to indi

cate an overcurrent fault has turned off the MOSFET. For

a given circuit breaker time delay

, the equation for setting

the timing capacitor’s value is as follows:

= T

• 0.083[µF/ms]

After the switch is turned off, the TIMER pin begins dis-

charging the timing capacitor with a 2µA pull-down cur-

rent. When the TIMER pin reaches its 0.2V threshold, the

switch is allowed to turn on again if the over

current fault

latch has been cleared. Bringing the UV pin below 0.6V for

a minimum of 1µs and then high will clear the fault latch.

Tying the F LT pin to the UV pin allows the part to self-clear

the fault and turn the MOSFET on as soon as TIMER pin has

ramped below 0.2V. In this auto retry mode, the LTC4218

repeatedly tries to turn on after an overcurrent at a period

determined by the capacitor on the TIMER pin.

The waveform in Figure 3 shows how the output latches

off following a short circuit. The drop across the sense

resistor is 3.75mV as the timer ramps up.

Figure 3. Short-Circuit Waveform

Current Limit Stability

The C

GATE

value is chosen to set the inrush current. The

GATE

value should be chosen to stabilize the current limit

large signal response. For most large MOSFETs 1k is a

suitable value. Smaller sized MOSFETs may require R

GATE

values up to 100k. To determine stability create a load

step using a resistive load equal to half supply divided by

the current limit value. Increase R

GATE

until the GATE pin

voltage is devoid of ringing during the load step.

Current Limit Adjustment

The default value of the active current limiting signal thresh

old is 15mV. The current limit threshold can be adjusted

lower by placing a resistor on the I

SET

pin. As shown in

the Functional Block Diagram the voltage at the I

SET

(via the clamp circuit) sets the CS ampliﬁer’s built-in offset

voltage. This offset voltage directly determines the active

current limit value. With the I

SET

pin open, the voltage at

the I

SET

pin is determined by the buffered reference volt-

age. This voltage is set to 0.618V which corresponds to

a 15mV current limit threshold.

An external R

SET

resistor placed between the I

SET

pin and

ground forms a resistive divider with the internal 20k R

ISET

sourcing resistor. The divider acts to lower the voltage at

the I

SET

pin and therefore lower the current limit threshold.

The overall current limit threshold precision is reduced

1ms/DIV

4218 F03

∆V

GATE

10V/DIV

OUT

2A/DIV

OUT

10V/DIV

TIMER

2V/DIV

LTC4218

4218fh

For more information www.linear.com/LTC4218

applications inForMation

to ±11% when using a 20k resistor to half the threshold.

This pin’s 20k sourcing impedance allows noise to couple

to this pin and disturb the current limit threshold. Place

a 0.1µF capacitor between the I

SET

pin and ground when

a board trace is connected to this pin.

Using a switch (connected to ground) in series with R

SET

allows the active current limit to change only when the

switch is closed. This feature can be used to program a

reduced running current while the maximum current limit

is used at start-up.

Monitor MOSFET Current

The current in the MOSFET passes through the sense

resistor. The voltage on the sense resistor is converted to

a current that is sourced out of the I

MON

pin. The gain of

the I

SENSE

ampliﬁer is 100µA from I

MON

for 15mV on the

sense resistor. This output current can be converted to a

voltage using an external resistor to drive a comparator

or ADC. The voltage compliance for the I

MON

pin is from

0V to INTV

– 0.7V.

A microcontroller with a built-in comparator can build a

simple integrating single-slope ADC by resetting a capaci-

tor that is charged with this current. When the capacitor

voltage trips the comparator and the capacitor is reset, a

timer is started. The time between resets will indicate the

MOSFET current.

Monitor OV and UV Faults

Protecting the load from an overvoltage condition is the

main function of the OV pin. In the LTC4218-12 an internal

resistive divider (driving the OV pin) connects to a compara

tor to turn off the MOSFET when the V

voltage exceeds

15.05V. If the V

pin subsequently falls back below 14.8V,

the switch will be allowed to turn on immediately. In the

LTC4218, the OV pin threshold is 1.235V when rising and

1.215V when falling out of overvoltage.

The UV pin functions as an undervoltage protection pin or

as an “on” pin. In the LTC4218-12 the MOSFET turns off

when V

falls below 9.23V. If the V

pin subsequently

rises above 9.88V for 100ms, the switch will be allowed

to turn on again. The LTC4218 UV turn on/off threshold

is 1.235V (rising) and 1.155V (falling).

In the case of an undervoltage or overvoltage, the MOSFET

turns off and there is indication on the PG status pin. When

the overvoltage is removed, the MOSFET’s gate ramps up

immediately.

Power Good Indication

In addition to setting the foldback current limit threshold,

the FB pin is used to determine a power good condition.

The LTC4218-12 uses an internal resistive divider on the

SOURCE pin to drive the FB pin. The PG comparator in

dicates logic high when SOURCE pin rises above 10.5V. If

the SOURCE pin subsequently falls below 10.3V

, the com-

parator toggles low. On the LTC4218, the PG comparator

drives high when the FB pin rises above 1.23V and low

when falls below 1.215V

Once the PG comparator is high, the GA

TE pin voltage

is monitored with respect to the SOURCE pin. Once the

GATE minus SOURCE voltage exceeds 4.2V, the PG pin

goes high. This indicates to the system that it is safe to

load the Output while the MOSFET is completely turned

“on”. The PG pin goes low when the GATE is commanded

off (using the UV, OV or SENSE

/SENSE

–

pins) or when

the PG comparator drives low.

12V Fixed Version

In the LTC4218-12, the UV, OV and FB pins are driven by

internal dividers which may need to be ﬁltered to prevent

false faults. By placing a bypass capacitor on these pins

the faults are delayed by the RC time constant. Use the R

value from the electrical table for this calculation.

In cases where the ﬁxed thresholds need a slight adjust

ment, placing a resistor from the UV or OV pins to V

or GND will adjust the threshold up or down. Likewise,

placing a resistor between FB pin to OUT or GND adjusts

the threshold. Again, use the R

value from the electrical

table for this calculation.

An example in Figure 4 raises the UV turn-on voltage from

9.88V to 10.5V. Increasing the UV level requires adding a

resistor between UV and ground. The resistor, (R

SHUNT1

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LTC4218CGN#TRPBF

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Hot Swap Voltage Controllers Low Voltage Hot Swap Controller with Adjustable Current Limit

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