514MLFT Datasheet 514MLF, 514MLFT | P1-P3

DATASHEET

LOCO™ PLL CLOCK GENERATOR ICS514

IDT™ / ICS™

LOCO™ PLL CLOCK GENERATOR 1

ICS514 REV G 051310

Description

The ICS514 LOCO

is the most cost effective way to

generate a high-quality, high-frequency clock output

from a 14.31818 MHz crystal or clock input. The name

LOCO stands for Low Cost Oscillator, as it is designed

to replace crystal oscillators in most electronic

systems. Using Phase-Locked Loop (PLL) techniques,

the device uses a standard, inexpensive crystal to

produce output clocks up to 66.66 MHz.

Stored in the chip’s ROM is the ability to generate five

different output frequencies, allowing one chip to work

in different speed processor systems.

The device also has a power-down mode that turns off

the clock outputs when both select pins are low. In this

mode, the internal PLL is not running.

Features

• Packaged as 8-pin SOIC or die

• Pb (lead) free package

• IDT’s lowest cost PLL clock plus reference

• Produces common computer frequencies

• Input crystal frequency typically 14.3182 MHz

• Output clock frequencies up to 66.66 MHz from a

14.3182 MHz crystal or input clock

• Low jitter of 50 ps (one sigma)

• Compatible with all popular CPUs

• Duty cycle of 45/55

• Custom frequencies available

• Operating voltage of 3.3 V to 5.5 V

• Power-down mode turns off chip

• 25 mA drive capability at TTL levels

• Advanced, low-power CMOS process

Block Diagram

CLK

PLL Clock

Synthesis

and Control

Circuitry

14.31818 MHz crystal

or clock input

GND

VDD

Crystal

Oscillator

S1:0

X1/ICLK

Optional crystal capacitors

REF

ICS514

LOCO™ PLL CLOCK GENERATOR CLOCK MULTIPLIER

IDT™ / ICS™

LOCO™ PLL CLOCK GENERATOR 2

ICS514 REV G 051310

Pin Assignment Clock Decoding Table (MHz) with 14.31818

MHz Crystal or Clock Input

0 = connect directly to ground

1 = connect directly to VDD

M = leave unconnected (floating)

CLK and REF stop low in power-down state

Pin Descriptions

Notes:

1. With S1 = S0 = 0, the internal PLL is turned off and the CLK outputs stops low. The crystal oscillator and

REF output are still active.

2. With a clock input, the phase relationship between the input and the output clocks can change each time

the device is powered on. If a fixed phase relationship is required, use the ICS571 or other zero delay

multipliers.

X1/ICLK

VDD

GND

REF

CLK

X21

8-pin (150 mil) SOIC

S1 S0 CLK Multiplier Accuracy

0 0 Power-down CLK — —

0 1 25 1.746 1 ppm

M 0 33.33 2.328 0.008%

M 1 40 2.794 1 ppm

1 0 50 3.492 1 ppm

1 1 66.66 4.656 0.008%

Number

Name

Type

Pin Description

1 XI/ICLK Input Crystal connection to a 14.31818 MHz crystal or clock input.

2 VDD Power Connect to +3.3 V or +5 V.

3 GND Power Connect to ground.

4 REF Output Reference 14.31818 MHz crystal oscillator buffered clock output.

5 CLK Output Clock output per table above.

6 S0 Tri-level Input Select 0 for output clock. Connect to GND or VDD or float. See

table above.

7 S1 Tri-level Input Select 1 for output clock. Connect to GND or VDD or float. See

table above.

8 X2 Output Crystal connection to a 14.31818 MHz crystal. Leave unconnected

for clock input.

ICS514

LOCO™ PLL CLOCK GENERATOR CLOCK MULTIPLIER

IDT™ / ICS™

LOCO™ PLL CLOCK GENERATOR 3

ICS514 REV G 051310

External Components

Decoupling Capacitor

As with any high-performance mixed-signal IC, the

ICS514 must be isolated from system power supply

noise to perform optimally.

A decoupling capacitor of 0.01µF must be connected

between VDD and the GND. It must be connected close

to the ICS514 to minimize lead inductance. No external

power supply filtering is required for the ICS514.

Series Termination Resistor

A 33Ω terminating resistor can be used next to the CLK

and REF pins for trace lengths over one inch.

Crystal Load Capacitors

The total on-chip capacitance is approximately 12 pF. A

parallel resonant, fundamental mode crystal should be

used. The device crystal connections should include

pads for small capacitors from X1 to ground and from

X2 to ground. These capacitors are used to adjust the

stray capacitance of the board to match the nominally

required crystal load capacitance. Because load

capacitance can only be increased in this trimming

process, it is important to keep stray capacitance to a

minimum by using very short PCB traces (and no vias)

between the crystal and device. Crystal capacitors, if

needed, must be connected from each of the pins X1

and X2 to ground.

The value (in pF) of these crystal caps should equal (C

-12 pF)*2. In this equation, C

= crystal load capacitance

in pF. Example: For a crystal with a 16 pF load

capacitance, each crystal capacitor would be 8 pF

[(16-12) x 2 = 8].

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the ICS514. These ratings, which

are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the

device at these or any other conditions above those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can

affect product reliability. Electrical parameters are guaranteed only over the recommended operating

temperature range.

Item Rating

Supply Voltage, VDD 7 V

All Inputs and Outputs (referenced to GND) -0.5 V to VDD+0.5 V

Ambient Operating Temperature 0 to +70° C

Storage Temperature -65 to +150° C

Soldering Temperature 260° C

P1-P3 P4-P6 P7-P7

514MLFT

Mfr. #:

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Manufacturer:

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Description:

Clock Generators & Support Products LOCO PLL CLOCK MULTIPLIER

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