STEP-UP OR DOWN, SINGLE-COIL, PWM CONTROL SWITCHING REGULATOR CONTROLLER
Rev.2.1_00
S-8460
Seiko Instruments Inc. 13
4. 1 Enhancement (N-channel) MOS FET
The EXT1 to EXT3 pins can directly drive an N-channel MOS FET with a gate capacitance of approximate 1000
pF.
When an N-channel MOS FET is used, efficiency will be 2 to 3% higher than that achieved by a PNP or an NPN
bipolar transistor since the MOS FET switching speed is faster than that of the bipolar transistor and power
dissipation due to the base current is avoided.
The important parameters in selecting a MOS FET are threshold voltage, breakdown voltage between gate and
source, breakdown voltage between drain and source, total gate capacitance, on-resistance, and the current rating.
Voltage swing of the EXT2 and EXT3 pins is between V
L
and V
SS
. The EXT1 pin voltage swings between V
IN
+ V
L
and V
IN
since the LX pin voltage becomes the input voltage (V
IN
) when SW2 is off. The breakdown voltage
between the gate and source of the transistors should be at least some volts higher than the V
L
voltage since the
maximum voltage applied between gate and source of each MOS FET is V
L
.
When V
IN
is lower than 4.5 V, the threshold voltage of MOS FETs should be low enough to turn on completely at
low input voltage since the V
L
voltage becomes V
IN
. Immediately after the power is turned on, or the shutdown
state at which the step-up and step-down operation is terminated, the input voltage or output voltage is applied
across the drain and the source of the MOS FETs. The transistors therefore need to have drain to source
breakdown voltage that is also several volts higher than the input voltage or output voltage.
The total gate capacitance and the on-resistance affect the efficiency.
The larger the total gate capacitance becomes and the higher the input voltage becomes, the more the power
dissipation for charging and discharging the gate capacitance by switching operation increases, and affects the
efficiency at low load current region. If the efficiency at low load is important, select MOS FETs with a small total
gate capacitance.
In regions where the load current is high, the efficiency is affected by power dissipation caused by the on-
resistance of the MOS FETs.
If the efficiency under heavy load is particularly important in the application, choose MOS FETs having on-
resistance as low as possible.
As for the current rating, select a MOS FET whose maximum continuous drain current rating is higher than the I
PK
.
If the external MOS FETs have much different characteristics (input capacitance, threshold value, etc.) among
them, they turn on at the same time to let a through current flow and reduce efficiency. If a MOS FET with a large
input capacitance is used, switching dissipation increases and efficiency decreases. If such a MOS FET is used
at several hundreds of mA or more, the dissipation at the MOS FET increases and may exceed the power
dissipation of the MOS FET. In selecting MOS FETs, thorough evaluation under the actual condition is
indispensable.
For reference, efficiency data using Sanyo CPH6401, CPH3403, and FTS2001, Vishay Siliconix Si2302DS, and
Fairchild Semiconductor FDN335N is attached in this document. Refer to “ Reference Data”.
In some MOS FETs current flow through the parasitic diode is not allowed. In this case, a Schottky diode must be
connected in parallel to the MOS FET. The Schottky diode must have a low forward voltage, a high switching
speed, a reverse-direction withstand voltage higher than the input/output voltage, and a current rating higher than
I
PK
.
