CPC7584
Rev. B www.clare.com 13
Preliminary
If presented with a short duration transient such as a
lightning event, the thermal shutdown feature will
typically not activate. But in an extended power-cross
transient, the device temperature will rise and the
thermal shutdown will activate forcing the switches to
the all-off state. At this point the current measured at
pin 3 (T
BAT
) and pin 14 (R
BAT
) will drop to zero. Once
the device enters thermal shutdown it will remain in
the all-off state until the temperature of the device
drops below the activation level of the thermal
shutdown circuit. This will return the device to the state
prior to thermal shutdown. If the transient has not
passed, current will flow at the value allowed by the
dynamic DC current limiting of the switches and
heating will begin again, reactivating the thermal
shutdown mechanism. This cycle of entering and
exiting the thermal shutdown mode will continue as
long as the fault condition persists. If the magnitude of
the fault condition is great enough, the external
secondary protector could activate and shunt all
current to ground.
The thermal shutdown mechanism of the CPC7584
can be disable by applying +V
DD
to pin 7 (TSD).
2.8 External Protection Elements
The CPC7584 requires only one overvoltage
secondary protector on the loop side of the device.
The integrated protection feature described above
negates the need for protection on the line side. The
secondary protector limits voltage transients to levels
that do not exceed the breakdown voltage or
input-output isolation barrier of the CPC7584. A
foldback or crowbar type protector is recommended to
minimize stresses on the device.
Consult Clare’s application note, AN-100, “Designing
Surge and Power Fault Protection Circuits for Solid
State Subscriber Line Interfaces” for equations related
to the specifications of external secondary protectors,
fused resistors and PTCs.
2.9 Data Latch
The CPC7584 has an integrated data latch. The latch
operation is controlled by logic-level input pin 11
(LATCH). The data input of the latch is pin 10 (IN
RING
)
and pin 9 (IN
TEST-IN
) of the device while the output of
the data latch is an internal node used for state
control. When LATCH control pin is at logic 0, the data
latch is transparent and data control signals flow
directly through to state control. A change in input will
be reflected in a change is switch state. When LATCH
control pin is at logic 1, the data latch is active and a
change in input control will not affect switch state. The
switches will remain in the position they were in when
the LATCH changed from logic 0 to logic 1 and will not
respond to changes in input as long as the latch is at
logic 1. The TSD input is not tied to the data latch.
Therefore, TSD is not affected by the LATCH input and
the TSD input will override state control via pin 10
(IN
RING
) and pin 9 (IN
TEST-IN
) and the LATCH.
