PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
Rev. 01 — 14 October 2002 Product data
1. Description
The PCKEL14 is a low skew 1:5 clock distribution chip designed explicitly for low
skew clock distribution applications. The device can be driven by either a differential
or single-ended ECL, or if positive power supplies are used, PECL input signal. The
PCKEL14 is designed to operate in ECL or PECL mode for a voltage supply range of
2.375 V to 3.8 V (or 2.375 V to 3.8 V).
The PCKEL14 features a multiplexed clock input to allow for the distribution of a lower
speed scan or test clock along with the high speed system clock. When LOW (or left
open and pulled LOW by the input pull-down resistor), the SEL pin will select the
differential clock input.
The common enable (EN) is synchronous, so that the outputs will only be
enabled/disabled when they are already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/disabled, as can happen
with an asynchronous control. The internal flip-flop is clocked on the falling edge of
the input clock, therefore all associated specification limits are referenced to the
negative edge of the clock input.
The V
BB
pin (an internally generated voltage supply) is available to this device only.
For single-ended conditions, the unused differential input is connected to V
BB
as a
switching reference voltage. V
BB
may also rebias AC-coupled inputs. When used,
decouple V
BB
and V
CC
via a 0.01 µF capacitor and limit current sourcing or sinking to
0.1 mA. When not used, V
BB
should be left open.
2. Features
50 ps output-to-output skew at 3.3 V
Synchronous enable/disable
Multiplexed clock input
ESD protection: > 2.5 kV HBM
The PCK series contains temperature compensation
PECL mode operating range: V
CC
= 2.375 V to 3.8 V, with V
EE
=0V
NECL mode operating range: V
CC
= 0 V, with V
EE
= 2.375 V to 3.8 V
Internal 75 k pull-down resistors on all inputs, plus a 37.5 k pull-up on CLK
Q output will default LOW with inputs open or at V
EE
Meets or exceeds JEDEC spec EIA/JESD78 IC latch-up test
Moisture sensitivity level 1
Flammability rating: UL-94 code V-0 @ 1/8”
Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
Product data Rev. 01 — 14 October 2002 2 of 15
9397 750 09564
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
3. Pinning information
3.1 Pinning
3.2 Pin description
3.2.1 Power supply connection
Fig 1. SO20 pin configuration. Fig 2. TSSOP pin configuration.
PCKEL14D
002aaa217
1
2
3
4
5
6
7
8
9
10
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
20
19
18
17
16
15
14
13
12
11
V
CC
EN
V
CC
NC
SCLK
CLK
CLK
V
BB
SEL
V
EE
PCKEL14PW
002aaa353
1
2
3
4
5
6
7
8
9
10
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
V
CC
EN
V
CC
NC
SCLK
CLK
CLK
V
BB
SEL
V
EE
20
19
18
17
16
15
14
13
12
11
Table 1: Pin description
Symbol Pin Description
Q0-Q4 1, 3, 5, 7, 9 ECL differential clock outputs, non-inverted
Q0-Q4 2, 4, 6, 8, 10 ECL differential clock outputs, inverted
V
EE
11 negative supply voltage
SEL 12 ECL clock select input
V
BB
13 reference voltage output
CLK 14 ECL differential clock input, inverted
CLK 15 ECL differential clock input, non-inverted
SCLK 16 ECL scan clock input
NC 17 no connect
EN 19 ECL synchronous enable, Active-LOW
V
CC
18, 20 positive supply voltage
CAUTION
All V
CC
and V
EE
pins must be connected to an appropriate power
supply to guarantee proper operation.
MSC895
Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
Product data Rev. 01 — 14 October 2002 3 of 15
9397 750 09564
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
4. Ordering information
5. Logic diagram
6. Function table
[1] On next negative transition of CLK or SCLK.
Table 2: Ordering information
Type number Package
Name Description Version
PCKEL14D SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
PCKEL14PW TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
Fig 3. Logic diagram.
CAUTION
All V
CC
and V
EE
pins must be connected to an appropriate power
supply to guarantee proper operation.
DQ
1
2
3
4
5
6
7
8
9
10
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
1
0
19
16
15
14
12
EN
SCLK
CLK
CLK
SEL
002aaa218
13
V
BB
MSC895
Table 3: Function table
X = Don’t care.
CLK SCLK SEL EN Q
LXLLL
HXLLH
XLHLL
XHHL H
XXXHL
[1]

PCKEL14PW,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC CLK BUFFER 2:5 1GHZ 20TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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