AOZ8904
Rev. 2.1 January 2011 www.aosmd.com Page 5 of 11
Application Information
The AOZ8904 TVS is design to protect four data lines
from fast damaging transient over-voltage by clamping it
to a reference. When the transient on a protected data
line exceed the reference voltage the steering diode is
forward bias thus, conducting the harmful ESD transient
away from the sensitive circuitry under protection.
PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8904 devices should be located as close as possible
to the noise source. The placement of the AOZ8904
devices should be used on all data and power lines that
enter or exit the PCB at the I/O connector. In most
systems, surge pulses occur on data and power lines
that enter the PCB through the I/O connector. Placing
the AOZ8904 devices as close as possible to the noise
source ensures that a surge voltage will be clamped
before the pulse can be coupled into adjacent PCB
traces. In addition, the PCB should use the shortest
possible traces. A short trace length equates to low
impedance, which ensures that the surge energy will be
dissipated by the AOZ8904 device. Long signal traces
will act as antennas to receive energy from fields that are
produced by the ESD pulse. By keeping line lengths as
short as possible, the efficiency of the line to act as an
antenna for ESD related fields is reduced. Minimize
interconnecting line lengths by placing devices with the
most interconnect as close together as possible. The
protection circuits should shunt the surge voltage to
either the reference or chassis ground. Shunting the
surge voltage directly to the IC’s signal ground can cause
ground bounce. The clamping performance of TVS
diodes on a single ground PCB can be improved by
minimizing the impedance with relatively short and wide
ground traces. The PCB layout and IC package parasitic
inductances can cause significant overshoot to the TVS’s
clamping voltage. The inductance of the PCB can be
reduced by using short trace lengths and multiple layers
with separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design. The AOZ8904 ultra-low
capacitance TVS is designed to protect four high speed
data transmission lines from transient over-voltages by
clamping them to a fixed reference. The low inductance
and construction minimizes voltage overshoot during
high current surges. When the voltage on the protected
line exceeds the reference voltage the internal steering
diodes are forward biased, conducting the transient
current away from the sensitive circuitry.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
1. Place the TVS near the IO terminals or connectors to
restrict transient coupling.
2. Fill unused portions of the PCB with ground plane.
3. Minimize the path length between the TVS and the
protected line.
4. Minimize all conductive loops including power and
ground loops.
5. The ESD transient return path to ground should be
kept as short as possible.
6. Never run critical signals near board edges.
7. Use ground planes whenever possible.
8. Avoid running critical signal traces (clocks, resets,
etc.) near PCB edges.
9. Separate chassis ground traces from components
and signal traces by at least 4mm.
10. Keep the chassis ground trace length-to-width ratio
<5:1 to minimize inductance.
11. Protect all external connections with TVS diodes.
