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LTC1821-1AIGW#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
7
LTC1821
I
OUT
(Pin 14): DAC Current Output. Normally tied through
a 22pF feedback capacitor in unipolar mode (15pF in
bipolar mode) to V
OUT
.
V
+
(Pin 15): Amplifier Positive Supply. Range is 4.5V to
16.5V.
AGNDS (Pin 16): Analog Ground Sense. Connect to
analog ground.
AGNDF (Pin 17): Analog Ground Force. Connect to
analog ground.
DNC (Pin 18, 19, 21): Connected internally. Do not
connect external circuitry to these pins.
V
–
(Pin 20): Amplifier Negative Supply. Range is –4.5V
to –16.5V.
NC (Pin 22): No Connection.
LD (Pin 23): DAC Digital Input Load Control Input. When
LD is taken to a logic high, data is loaded from the input
register into the DAC register, updating the DAC output.
WR (Pin 24): DAC Digital Write Control Input. When WR
is taken to a logic low, data is written from the digital input
pins into the 16-bit wide input reigster.
D15 (Pins 25): MSB or Digital Input Data Bit 15.
D14 (Pin 26): Digital Input Data Bit 14.
D13 (Pin 27): Digital Input Data Bit 13.
D12 (Pin 28): Digital Input Data Bit 12.
D11 (Pin 29): Digital Input Data Bit 11.
D10 (Pin 30): Digital Input Data Bit 10.
D9 (Pin 31): Digital Input Data Bit 9.
D8 (Pin 32): Digital Input Data Bit 8.
D7 (Pin 33): Digital Input Data Bit 7.
D6 (Pin 34): Digital Input Data Bit 6.
D5 (Pin 35): Digital Input Data Bit 5.
D4 (Pin 36): Digital Input Data Bit 4.
DGND (Pin 1): Digital Ground. Connect to analog ground.
V
CC
(Pin 2): Positive Supply Input. 4.5V ≤ V
CC
≥ 5.5V.
Requires a bypass capacitor to ground.
D3 (Pin 3): Digital Input Data Bit 3.
D2 (Pin 4): Digital Input Data Bit 2.
D1 (Pin 5): Digital Input Data Bit 1.
D0 (Pin 6): LSB or Digital Input Data Bit 0.
CLR (Pin 7): Digital Clear Control Function for the DAC.
When CLR is taken to a logic low, it sets the DAC output
and all internal registers to: zero code for the LTC1821 and
midscale code for the LTC1821-1.
REF (Pin 8): Reference Input and 4-Quadrant Resistor R2.
Typically ±10V, accepts up to ±15V. In 2-quadrant mode,
tie this pin to the external reference signal. In 4-quadrant
mode, this pin is driven by external inverting reference
amplifier.
R
COM
(Pin 9): Center Tap Point of the Two 4-Quadrant
Resistors R1 and R2. Normally tied to the inverting input
of an external amplifier in 4-quadrant operation. Other-
wise this pin is shorted to the REF pin. See Figures 1
and 2.
R1 (Pin 10): 4-Quadrant Resistor R1. In 2-quadrant
operation, short this pin to the REF pin. In 4-quadrant
mode, tie this pin to the external reference signal.
R
OFS
(Pin 11): Bipolar Offset Resistor. Typically swings
±10V, accepts up to ±15V. For 2-quadrant operation, tie
this pin to R
FB
and for 4-quadrant operation, tie this pin to
R1.
R
FB
(Pin12): Feedback Resistor. Normally connected to
V
OUT
. Typically swings ±10V. The voltage at this pin
swings 0 to V
REF
in unipolar mode and ±V
REF
in bipolar
mode.
V
OUT
(Pin 13): DAC Voltage Output. Normally connected
to R
FB
and to I
OUT
through a 22pF feedback capacitor in
unipolar mode (15pF in bipolar mode). Typically swings
±10V.
PIN FUNCTIONS
UUU
8
LTC1821
Table 1
CONTROL INPUTS
CLR WR LD REGISTER OPERATION
0 X X Reset Input and DAC Register to All 0s for LTC1821 and Midscale for LTC1821-1 (Asynchronous Operation)
1 0 0 Write Input Register with All 16 Data Bits
1 1 1 Load DAC Register with the Contents of the Input Register
1 0 1 Input and DAC Register Are Transparent
1 CLK = LD and WR Tied Together. The 16 Data Bits Are Written Into the Input Register on the Falling Edge of the CLK and Then
Loaded Into the DAC Register on the Rising Edge of the CLK
1 1 0 No Register Operation
TRUTH TABLE
96k
12k
12k
96k
48k
96k
48k
96k
DECODER
D15
(MSB)
D13
D14
D15
D12 D11 D0
(LSB)
LOAD
V
CC
REF R
FB
V
OUT
I
OUT
DNC*
CLR
7
DGND
*CONNECTED INTERNALLY.
DO NOT CONNECT EXTERNAL
CIRCUITRY TO THESE PINS
1
1821 BD
DAC REGISTER
48k 48k 48k 48k 48k 48k 48k
12k
23
2
R1
10
R
COM
9
8
LD
24
25
D14
26
D4
36
D3
3
D2
4
D0
6
D1
5
WR
18
NC
22
13
DNC*
19
DNC*
21
V
+
15
14
V
–
20
AGNDS
16
AGNDF
17
12
R
OFS
11
• • •
12k
WR
INPUT REGISTER
• • • •
RST
RST
–
+
BLOCK DIAGRA
W
9
LTC1821
Description
The LTC1821 is a 16-bit voltage output DAC with a full
parallel 16-bit digital interface. The device can operate
from 5V and ±15 supplies and provides both unipolar 0V
to – 10V or 0V to 10V and bipolar ±10V output ranges from
a 10V or –10V reference input. Additionally, the power
supplies for the LTC1821 can go as low as 4.5V and ±4.5V.
In this case for a 2.5V or –2.5V reference, the output range
is 0V to –2.5V, 0V to 2.5V and ±2.5V. The LTC1821 has
three additional precision resistors on chip for bipolar
operation. Refer to the block diagram regarding the fol-
lowing description.
The 16-bit DAC consists of a precision R-2R ladder for the
13 LSBs. The three MSBs are decoded into seven seg-
ments of resistor value R. Each of these segments and the
R-2R ladder carries an equally weighted current of one
eighth of full scale. The feedback resistor R
FB
and
4-quadrant resistor R
OFS
have a value of R/4. 4-quadrant
resistors R1 and R2 have a magnitude of R/4. R1 and R2
together with an external op amp (see Figure 2) inverts the
reference input voltage and applies it to the 16-bit DAC
input REF, in 4-quadrant operation. The REF pin presents
a constant input impedance of R/8 in unipolar mode and
R/12 in bipolar mode.
The LTC1821 contains an onboard precision high speed
amplifier. This amplifier together with the feedback resis-
tor (R
FB
) form a precision current-to-voltage converter for
the DAC’s current output. The amplifier has very low noise,
offset, input bias current and settles in less than 2µs to
0.0015% for a 10V step. It can sink and source 22mA
(±15V) typically and can drive a 300pF capacitive load. An
added feature of these devices, especially for waveform
generation, is a proprietary deglitcher that reduces glitch
impulse to below 2nV-s over the DAC output voltage range.
Digital Section
The LTC1821 has a 16-bit wide full parallel data bus input.
The device is double-buffered with two 16-bit registers.
The double-buffered feature permits the update of several
DACs simultaneously. The input register is loaded directly
from a 16-bit microprocessor bus when the WR pin is
brought to a logic low level. The second register (DAC
register) is updated with the data from the input register
when the LD signal is brought to a logic high. Updating the
DAC register updates the DAC output with the new data. To
make both registers transparent in flowthrough mode, tie
WR low and LD high. However, this defeats the deglitcher
operation and output glitch impulse may increase. The
deglitcher is activated on the rising edge of the LD pin. The
APPLICATIONS INFORMATION
WUU
U
DATA
LD
CLR
1821 TD
t
WR
t
DS
t
LD
t
DH
t
LWD
WR
t
CLR
TI I G DIAGRA
UWW
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LTC1821-1AIGW#PBF

Mfr. #:
Buy LTC1821-1AIGW#PBF
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 16-B, Ultra Precise, Fast Settling VOUT
Lifecycle:
New from this manufacturer.
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