M68AW031A
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OPERATION
The M68AW031A has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E
=High).
An Output Enable (G
) signal provides a high
speed tri-state control, allowing fast read/write cy-
cles to be achieved with the common I/O data bus.
Operational modes are determined by device con-
trol inputs W
and E as summarized in the Operat-
ing Modes table (see Table 2).
Table 2. Operating Modes
Note: X = V
IH
or V
IL
.
Read Mode
The M68AW031A is in the Read mode whenever
Write Enable (W
) is High with Output Enable (G)
Low, and Chip Enable (E
) is asserted. This pro-
vides access to data of the 262,144 locations in
the static memory array, specified by the 15 ad-
dress inputs. Valid data will be available at the
eight output pins within t
AVQV
after the last stable
address, providing G
is Low and E is Low. If Chip
Enable or Output Enable access times are not
met, data access will be measured from the limit-
ing parameter (t
ELQV
or t
GLQV
) rather than the ad-
dress. Data out may be indeterminate at t
ELQX
and
t
GLQX
but data lines will always be valid at t
AVQV
.
See Figures 9, 10, 11 and Table 7 for details on
Read mode AC timings and Characteristics.
Write Mode
The M68AW031A is in the Write mode whenever
the W
and E are Low. Either the Chip Enable input
(E
) or the Write Enable input (W) must be de-
asserted during Address transitions for
subsequent write cycles. When E
(W) is Low, write
cycle begins on the W
(E)'s falling edge.
Therefore, address setup time is referenced to
Write Enable or Chip Enable as t
AVWL
and t
AVEL
respectively, and is determined by the latter
occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E
or W.
If the Output is enabled (E
= Low, G = Low), then
W
will return the outputs to high impedance within
t
WLQZ
of its falling edge. Care must be taken to
avoid bus contention in this type of operation. Data
input must be valid for t
DVWH
before the rising
edge of Write Enable, or for t
DVEH
before the rising
edge of E
, whichever occurs first, and remain valid
for t
WHDX
and t
EHDX
respectively.
See Figures 12, 10 and Table 8 for details on Write
mode AC timings and Characteristics.
Operation E W G DQ0-DQ7 Power
Deselected
V
IH
X X Hi-Z
Standby (I
SB
)
Read
V
IL
V
IH
V
IL
Data Output
Active (I
CC
)
Write
V
IL
V
IL
X Data Input
Active (I
CC
)
Output Disabled
V
IL
V
IH
V
IH
Hi-Z
Active (I
CC
)
