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AD9763-EBZ
P1-P3
P4-P6
P7-P9
P10-P12
–7–
AN-555
REV. 0
3
4
5
6
7
8
9
2
RP16
10
1
R1
R9
RCOM
22
INP1
INP2
INP3
INP4
INP5
INP6
INP7
INP8
3
4
5
6
7
8
9
2
RP9
10
1
R1
R9
RCOM
22
INP9
INP10
INP11
INP12
INP13
INP14
INCK1
3
4
5
6
7
8
9
2
RP10
10
1
R1
R9
RCOM
22
INP23
INP24
INP25
INP26
INP27
INP28
INP29
INP30
3
4
5
6
7
8
9
2
RP15
10
1
R1
R9
RCOM
22
INP31
INP32
INP33
INP34
INP35
INP36
INCK2
J
CLK
Q
Q
PRE
CLR
U1
12
11
9
7
10
14
DGND;8
DVDD;16
TSSOP112
13
K
1
2
C7
0.1
m
F
1
2
C8
0.01
m
F
DVDD
TP29
WHT
TP30
TP31
TP32
DGND;3,4,5
DGND;3,4,5
DGND;3,4,5
DGND;3,4,5
S1
S2
S3
S4
WRT1IN
IQWRT
CLK1IN
IQCLK
CLK2IN
RESET
WRT2IN
IQSEL
1
2
R1
50
V
1
2
R2
50
V
1
2
R3
50
V
1
2
R4
50
V
1
2
3
A
B
JP5
JP16
1
2
3
A
B
JP4
1
2
3
A
B
JP3
1
2
3
A
B
DCLKIN1
DCLKIN2
1
3
5
4
15
DGND;8
DVDD;16
TSSOP112
1
2
3
A
B
JP7
JP1
DVDD
1
2
3
A
B
JP6
DVDD
/2 CLOCK DIVIDER
WRT1
CLK1
CLK2
WRT2
TP33
SLEEP
1
2
R13
50
V
SLEEP
JP2
2
Q
J
CLK
Q
PRE
U1
CLR
6
K
DVDD
WHT
WHT
WHT
WHT
I
C
IC
I
C
JP9
TP10
B1
BAN-JACK
DVDDIN
L1
BEAD
1
2
C9
10
m
F
25V
TP37
TP38
TP43
TP39
DGND
DVDD
B2
BAN-JACK
BLK
BLK
BLK
BLK
RED
TP11
B3
BAN-JACK
AVDDIN
L2
BEAD
1
2
C10
10
m
F
25V
TP40
TP41
TP44
TP42
AGND
AVDD
B4
BAN-JACK
BLK
BLK
BLK
BLK
RED
POWER DECOUPLING AND INPUT CLOCKS
Figure 10.
Power Decoupling and Clocks on Dual DAC Evaluation Board
–8–
AN-555
REV. 0
11
6
RP5, 10
V
31
4
RP5, 10
V
51
2
RP5, 10
V
71
0
RP5, 10
V
11
6
RP6, 10
V
31
4
RP6, 10
V
51
2
RP6, 10
V
21
5
13
11
9
15
13
11
RP3
10
9
8
7
6
5
4
3
2
1
R1
DVDD
R9
RCOM
22
RP5, 10
V
4
RP5, 10
V
6
RP5, 10
V
8
RP5, 10
V
2
RP6, 10
V
4
RP6, 10
V
6
RP6, 10
V
89
RP6, 10
V
DUTP1
RP1
10
9
8
7
6
5
4
3
2
1
R1
DVDD
R9
RCOM
22
RP13
10
9
8
7
6
5
4
3
2
1
R1
R9
RCOM
33
RP11
10
9
8
7
6
5
4
3
2
1
R1
R9
RCOM
33
DUTP2
DUTP3
DUTP4
DUTP5
DUTP6
DUTP7
DUTP8
DUTP9
DUTP10
DUTP11
DUTP12
DUTP13
DUTP14
DCLKIN1
2 P1
P1
1
4 P1
P1
3
6 P1
P1
5
8 P1
P1
7
10
P1
P1
9
12
P1
P1
11
14
P1
P1
13
16 P1
P1
15
18 P1
P1
17
20 P1
P1
19
22 P1
P1
21
24 P1
P1
23
26 P1
P1
25
28 P1
P1
27
30 P1
P1
29
32 P1
P1
31
34 P1
P1
33
36 P1
P1
35
38 P1
P1
37
40 P1
P1
39
11
6
RP7, 10
V
31
4
RP7, 10
V
51
2
RP7, 10
V
71
0
RP7, 10
V
11
6
RP8, 10
V
31
4
RP8, 10
V
51
2
RP8, 10
V
21
5
13
11
9
15
13
11
RP4
10
9
8
7
6
5
4
3
2
1
R1
DVDD
R9
RCOM
22
RP7, 10
V
4
RP7, 10
V
6
RP7, 10
V
8
RP7, 10
V
2
RP8, 10
V
4
RP8, 10
V
6
RP8, 10
V
89
RP8, 10
V
DUTP23
RP2
9
8
7
6
5
4
3
2
1
R1
DVDD
R9
RCOM
22
10
RP14
10
9
8
7
6
5
4
3
2
1
R1
R9
RCOM
33
RP12
10
9
8
7
6
5
4
3
2
1
R1
R9
RCOM
33
DUTP24
DUTP25
DUTP26
DUTP27
DUTP28
DUTP29
DUTP30
DUTP31
DUTP32
DUTP33
DUTP34
DUTP35
DUTP36
DCLKIN2
71
0
RP5, 10
V
71
0
RP8, 10
V
SPARES
2 P2
P2
1
4 P2
P2
3
6 P2
P2
5
8 P2
P2
7
10
P2
P2
9
12
P2
P2
11
14
P2
P2
13
16 P2
P2
15
18 P2
P2
17
20 P2
P2
19
22 P2
P2
21
24 P2
P2
23
26 P2
P2
25
28 P2
P2
27
30 P2
P2
29
32 P2
P2
31
34 P2
P2
33
36 P2
P2
35
38 P2
P2
37
40 P2
P2
39
INP1
INP2
INP3
INP4
INP5
INP6
INP7
INP8
INP9
INP10
INP11
INP12
INP13
INP14
INCK1
INP23
INP24
INP25
INP26
INP27
INP28
INP29
INP30
INP31
INP32
INP33
INP34
INP35
INP36
INCK2
DIGITAL INPUT SIGNAL CONDITIONING
Figure 11.
Digital Input Signal Conditioning
–9–
AN-555
REV. 0
TP46
WHT
12
R14
256
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DB13
P1 (MSB)
DB12
P1
DB11
P1
DB10
P1
DB9
P1
DB8
P1
DB7
P1
DB6
P1
DB5
P1
DB4
P1
DB3
P1
DB2
P1
DB1
P1
DB0
P1
DCOM1
DVDD1
WRT1
CLK1
CLK2
WRT2
DCOM2
DVDD2
DB13
P2 (MSB)
DB12
P2
MODE
AVDD
IA1
IB1
FSADJ1
REFIO
GAINCTRL
FSADJ2
IA2
IB2
ACOM
SLEEP
DB0
P2
DB1
P2
DB2
P2
DB3
P2
DB4
P2
DB5
P2
DB6
P2
DB7
P2
DB8
P2
DB9
P2
DB10
P2
DB11
P2
U2
AD9763/
AD9765/
AD9767
1
2
C1
VAL
1
2
C2
0.01
m
F
1
2
C3
0.1
m
F
DVDD
1
2
3
AB
JP8
AVDD
1
2
C11
VAL
1
2
C12
0.01
m
F
1
2
C13
0.1
m
F
AVDD
SLEEP
DUTP36
DUTP35
DUTP34
DUTP33
DUTP32
DUTP31
DUTP30
DUTP29
DUTP28
DUTP27
DUTP26
DUTP25
1
2
C15
10pF
1
2
R7
50
V
1
2
C6
10pF
1
2
R8
50
V
WRT1
CLK1
CLK2
WRT2
DUTP23
DUTP24
DUTP1
DUTP2
DUTP3
DUTP4
DUTP5
DUTP6
DUTP7
DUTP8
DUTP9
DUTP10
DUTP11
DUTP12
DUTP13
DUTP14
1
2
C4
10pF
1
2
R5
50
V
1
2
C5
10pF
1
2
R6
50
V
TP34
WHT
R11
VAL
1:
1
3
2
16
4
NC = 5
T1
AGND;3,4,5
S6
OUT1
TP36
WHT
REFIO
1
2
C14
0.1
m
F
TP35
WHT
R12
VAL
1:
1
3
2
16
4
NC = 5
T2
AGND;3,4,5
S11
OUT2
DUT AND ANALOG OUTPUT SIGNAL CONDITIONING
BL4
BL3
12
R10
1.92k
V
C17
22nF
2
1
JP10
TP45
WHT
1
2
R9
1.92k
V
12
R15
256
V
2
1
C16
22nF
BL1
BL2
MODE1
1
2
3
AB
AVDD
ACOM
JP15
Figure 12.
Output Signal Conditioning
P1-P3
P4-P6
P7-P9
P10-P12
AD9763-EBZ
Mfr. #:
Buy AD9763-EBZ
Manufacturer:
Analog Devices Inc.
Description:
BOARD EVAL FOR AD9763
Lifecycle:
New from this manufacturer.
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