IR3651STRPBF Datasheet IR3651STRPBF, 111-3053PBF | P16-P18

IR3651SPBF

06/08/2011

To cancel one of the LC filter poles, place the

zero before the LC filter resonant frequency pole:

Using equations (15) and (16) to calculate C

4

.

One more capacitor is sometimes added in

parallel with C

4

and R

3

. This introduces one more

pole which is mainly used to suppress the

switching noise.

The additional pole is given by:

The pole sets to one half of switching frequency

which results in the capacitor C

POLE

:

For a general solution for unconditionally stability

for any type of output capacitors, in a wide range

of ESR values we should implement local

feedback with a compensation network (typeIII).

The typically used compensation network for

voltage-mode controller is shown in figure 15.

In such configuration, the transfer function is

given by:

The error amplifier gain is independent of the

transconductance under the following condition:

By replacing Z

in

and Z

f

according to figure 15, the

transformer function can be expressed as:

-(16

)

-

CL2

1

750F

F75F

oo

z

LCz

*

*.

%

π

=

As known, transconductance amplifier has high

impedance (current source) output, therefore,

consideration should be taken when loading the

error amplifier output. It may exceed its

source/sink output current capability, so that the

amplifier will not be able to swing its output

voltage over the necessary range.

The compensation network has three poles and

two zeros and they are expressed as follows:

Cross over frequency is expressed as:

CC

R2

1

F

POLE4

3

P

+

=

*

**

π

2

F

F For

FR*

1

C

1

FR

1

C

s

P

s3

4

s3

POLE

<<

≅

−

=

*

**

π

Fig.15: Compensation network with local

feedback and its asymptotic gain plot

INm

fm

o

e

Zg1

V

+

−

=

(

)

[]

)(*

*

*)(

*

)(

710

34

3

108743

348

CsR1

CC

sR1

RRsC1CsR1

CCsR

1

sH

+

⎥

⎦

⎤

⎢

⎣

⎡

⎟

⎠

⎞

⎜

⎝

⎛

+

++

+

=

871087

2z

43

1z

33

34

3

3P

710

2P

1P

RC2

1

RRC2

1

F

CR2

1

F

CR2

1

CC

R2

1

F

CR2

1

F

0F

**)(**

**

*

**

ππ

π

≅

+

=

≅

⎟

⎠

⎞

⎜

⎝

⎛

+

=

ooosc

in

73o

CL2

1

V

CRF

**

***

π

=

-(17)- 1Z*g and 1Z*g

inmfm

>>>>

V

O

V

REF

R

9

R

8

R

10

C

7

C

3

C

4

R

3

Ve

F

Z

1

F

Z

2

F

P

2

F

P

3

E/A

Z

f

Z

IN

Frequency

Gain(dB)

H(s) dB

Fb

Comp

16

IR3651SPBF

06/08/2011

Based on the frequency of the zero generated by

output capacitor and its ESR versus crossover

frequency, the compensation type can be

different. The table below shows the

compensation types and location of crossover

frequency.

The following design rules will give a crossover

frequency approximately one-tenth of the

switching frequency. The higher the band width,

the potentially faster the load transient response.

The DC gain will be large enough to provide high

DC-regulation accuracy (typically -5dB to -12dB).

The phase margin should be greater than 45

o

for

overall stability.

Desired Phase Margin:

Ceramic

F

LC

<F

o

<F

s/2

<F

ESR

TypeIII(PID)

Method B

Tantalum,

ceramic

F

LC

<F

o

<F

ESR

<F

s/2

TypeIII(PID)

Method A

Electrolytic

, Tantalum

F

LC

<F

ESR

<F

o

<F

s/2

TypII(PI)

Output

capacitor

F

ESR

vs. F

o

Compensator

type

R

VV

V

R

FC2

1

R

;

FC2

1

R

R and R R Calculate

VR

VCLF2

C

RF2

1

C

;

RF*2

1

C

:C and C ,C Calculate

8

refo

ref

9

10

2Z7

8

2P7

10

9810

in3

oscooo

7

33P

3

Z1

4

734

;*

;

**

:,

;

*

****

;

**

*

−

=

−=

=

π

3

π

Θ

=

max

Table1- The compensation type and location

of F

ESR

versus F

o

The details of these compensation types are

discussed in application note AN-1043 which can

be downloaded from IR Web-Site.

For F

LC

<F

o

<F

s/2

<F

ESR

typeIII method B is selected to place the pole and

zeros.

(

)

soESRo

F1/10~1/5F and FF *≤<

;

g

2

R

F*0.5F and F50F Select

Sin1

FF

Sin1

FF

m

3

sP32ZZ1

o2P

o2Z

≥

==

−

+

=

+

−

=

*.:

*

Θ

Programming the Current-Limit

The Current-Limit threshold can be set by

connecting a resistor (R

SET

) from drain of low

side MOSFET to the OCSet pin. The resistor

can be calculated by using equation (3).

The R

DS(on)

has a positive temperature

coefficient and it should be considered for the

worse case operation. This resistor must be

placed close to the IC, place a small ceramic

capacitor from this pin to ground for noise

rejection purposes.

)3 --(

R

IR

II

onDS

OCSetOCSet

criticalLSET

)(

∗

==

17

IR3651SPBF

06/08/2011

Layout Consideration

The layout is very important when designing high

frequency switching converters. Layout will affect

noise pickup and can cause a good design to

perform with less than expected results.

Start to place the power components, make all

the connection in the top layer with wide, copper

filled areas.

The inductor, output capacitor and the MOSFET

should be close to each other as possible. This

helps to reduce the EMI radiated by the power

traces due to the high switching currents through

them. Place input capacitor directly to the drain of

the high-side MOSFET, to reduce the ESR

replace the single input capacitor with two

parallel units

.

The feedback part of the system should be kept

away from the inductor and other noise sources.

The critical bypass components such as

capacitors for Vcc, DRVc and Vb should be close

to respective pins. It is important to place the

feedback components including feedback

resistors and compensation components close to

Fb and Comp pins.

In multilayer PCB use one layer as power ground

plane and have a control circuit ground (analog

ground), to which all signals are referenced. The

goal is to localize the high current path to a

separate loop that does not interfere with the

more sensitive analog control function. These two

grounds must be connected together on the PC

board layout at a single point.

18

Part Marking Information

IR3651STRPBF

IR3651STRPBF

Products related to this Datasheet