NJW1110
– 5 –
!CHARACTERISTICS OF BUS LINES (SDA,SCL) FOR I
2
C-BUS DEVICES
Standard mode
Fast mode
PARAMETER SYMBOL
MIN. TYP. MAX. MIN. TYP. MAX.
UNIT
SCL clock frequency f
SCL
- - 100 - - 400 kHz
Hold time (repeated) START condition.
t
HD:STA
4.0 - - 0.6 - - µs
Low period of the SCL clock t
LOW
4.7 - - 1.3 - - µs
High period of the SCL clock t
HIGH
4.0 - - 0.6 - - µs
Set-up time for a repeated START condition t
SU:STA
4.7 - - 0.6 - - µs
Data hold time
NOTE)
t
HD:DAT
0 - - 0 - - µs
Data set-up time t
SU:DAT
250 - - 100 - - ns
Rise time of both SDA and SCL signals t
r
- - 1000 - - 300 ns
Fall time of both SDA and SCL signals t
f
- - 300 - - 300 ns
Set-up time for STOP condition t
SU:STO
4.0 - - 0.6 - - µs
Bus free time between a STOP and START condition t
BUF
4.7 - - 1.3 - - µs
Capacitive load for each bus line C
b
- - 400 - - 400 pF
Noise margin at the Low level V
nL
0.5 - - 0.5 - - V
Noise margin at the High level
V
nH
1 - - 1 - -
V
C
b
; total capacitance of one bus line in pF.
NOTE). Data hold time : t
HD:DAT
Please hold the Data Hold Time (t
HD:DAT
) to 300ns or more to avoid status of unstable at SCL falling edge.
The SDA block in the NJW1110 does not hold data. Add external data-delay-circuit of the SDA terminal, in case of not
providing a hold time of at least 300nsec for the SDA in the master device.
The time-consists of the data-delay-circuit of the SDA terminal are as follows.
(a) Low level ! High level : T
LH
≈ R
P
*C
D
(b) High level ! Low level : T
HL
≈ R
D
*C
D
In addition, Schottky barrier diode (SBD) influences a Low level at the Acknowledge. Therefore choose the low forward
voltage (Vf) as much as possible.
MA STER
SCL
SDA
V
DD
R
P
R
P
R
D
SBD
C
D
NJW1110
